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Searched refs:FPU (Results 1 – 25 of 149) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/MBlaze/
Dimm.ll6 ; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
12 ; FPU: retimm_i8:
13 ; FPU: rtsd
14 ; FPU-NEXT: add
22 ; FPU: retimm_i16:
23 ; FPU: rtsd
24 ; FPU-NEXT: add
32 ; FPU: retimm_i32:
33 ; FPU: add
34 ; FPU-NEXT: rtsd
[all …]
Dfpu.ll2 ; FPU is not available in the hardware and that function calls are not used
3 ; when the FPU is available in the hardware.
6 ; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
10 ; FPU: test_add:
14 ; FPU-NOT: brlid
18 ; FPU: rtsd
20 ; FPU-NEXT: fadd
25 ; FPU: test_sub:
29 ; FPU-NOT: brlid
33 ; FPU: rtsd
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZScheduleZ196.td78 def : WriteRes<FPU, [Z196_FPUnit]>;
83 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
713 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
714 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
739 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
743 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
744 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
749 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
751 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
752 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
DSystemZScheduleZEC12.td79 def : WriteRes<FPU, [ZEC12_FPUnit]>;
84 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
751 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
752 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
777 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
781 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
782 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
787 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
789 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
790 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
/external/elfutils/tests/
Drun-addrcfi.sh68 FPU-control reg37 (%fctrl): undefined
69 FPU-control reg38 (%fstat): undefined
70 FPU-control reg39 (%mxcsr): undefined
115 FPU-control reg37 (%fctrl): undefined
116 FPU-control reg38 (%fstat): undefined
117 FPU-control reg39 (%mxcsr): undefined
334 FPU reg32 (f0): undefined
335 FPU reg33 (f1): undefined
336 FPU reg34 (f2): undefined
337 FPU reg35 (f3): undefined
[all …]
/external/llvm/test/MC/Mips/
Dupdate-module-level-options.s6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dset-oddspreg-nooddspreg-error.s6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dnooddspreg-error.s9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dupdate-module-level-options.s6 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
14 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dset-oddspreg-nooddspreg-error.s6 # CHECK-NOT: :[[@LINE-1]]:{{[0-9]+}}: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK: :[[@LINE-1]]:9: error: -mno-odd-spreg prohibits the use of odd FPU registers
Dnooddspreg-error.s9 # CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers
10 # CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMELFStreamer.cpp86 void emitFPU(unsigned FPU) override;
206 void ARMTargetAsmStreamer::emitFPU(unsigned FPU) { in emitFPU() argument
207 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; in emitFPU()
277 unsigned FPU; member in __anon2a1facbf0111::ARMTargetELFStreamer
381 void emitFPU(unsigned FPU) override;
396 : ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::FK_INVALID), in ARMTargetELFStreamer()
790 FPU = Value; in emitFPU()
793 switch (FPU) { in emitFPUDefaultAttributes()
919 report_fatal_error("Unknown FPU: " + Twine(FPU)); in emitFPUDefaultAttributes()
956 if (FPU != ARM::FK_INVALID) in finishAttributeSection()
[all …]
/external/llvm/test/CodeGen/ARM/
Dbuild-attributes.ll64 …e=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-FP16
65 …inux-gnueabi -mattr=-neon,+vfp3,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-D16-FP16
66 …linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD
67 …bi -mattr=-neon,+vfp3,+fp-only-sp,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD-FP16
68 …-mtriple=armv7-linux-gnueabi -mattr=+neon,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-NEON-FP16
200 ;; The default choice made by llc is for a V6 CPU without an FPU.
203 ;; FPU support!
219 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
234 ;; The default choice made by llc is for a V6M CPU without an FPU.
237 ;; FPU support!
[all …]
/external/llvm/lib/Support/
DTargetParser.cpp549 static StringRef getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
550 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
563 .Default(FPU); in getFPUSynonym()
648 unsigned llvm::ARM::parseFPU(StringRef FPU) { in parseFPU() argument
649 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
782 unsigned llvm::AArch64::parseFPU(StringRef FPU) { in parseFPU() argument
783 return ARM::parseFPU(FPU); in parseFPU()
/external/swiftshader/third_party/llvm-subzero/lib/Support/
DTargetParser.cpp549 static StringRef getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
550 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
563 .Default(FPU); in getFPUSynonym()
649 unsigned llvm::ARM::parseFPU(StringRef FPU) { in parseFPU() argument
650 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
785 unsigned llvm::AArch64::parseFPU(StringRef FPU) { in parseFPU() argument
786 return ARM::parseFPU(FPU); in parseFPU()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dbuild-attributes.ll69 …e=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-FP16
70 …inux-gnueabi -mattr=-neon,+vfp3,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-D16-FP16
71 …linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD
72 …bi -mattr=-neon,+vfp3,+fp-only-sp,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD-FP16
73 …-mtriple=armv7-linux-gnueabi -mattr=+neon,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-NEON-FP16
250 ;; The default choice made by llc is for a V6 CPU without an FPU.
253 ;; FPU support!
264 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
284 ;; The default choice made by llc is for a V6M CPU without an FPU.
287 ;; FPU support!
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMELFStreamer.cpp99 void emitFPU(unsigned FPU) override;
234 void ARMTargetAsmStreamer::emitFPU(unsigned FPU) { in emitFPU() argument
235 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; in emitFPU()
306 unsigned FPU = ARM::FK_INVALID; member in __anonf511ea170111::ARMTargetELFStreamer
410 void emitFPU(unsigned FPU) override;
896 FPU = Value; in emitFPU()
900 switch (FPU) { in emitFPUDefaultAttributes()
1026 report_fatal_error("Unknown FPU: " + Twine(FPU)); in emitFPUDefaultAttributes()
1065 if (FPU != ARM::FK_INVALID) in finishAttributeSection()
1128 FPU = ARM::FK_INVALID; in finishAttributeSection()
/external/llvm/include/llvm/Support/
DTargetParser.h134 unsigned parseFPU(StringRef FPU);
196 unsigned parseFPU(StringRef FPU);
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td50 // Mips 32-bit FPU Registers
53 // Mips 64-bit (aliased) FPU Registers
155 /// Mips Single point precision FPU Registers
163 /// Mips Double point precision FPU Registers (aliased
170 /// Mips Double point precision FPU Registers in MFP64 mode.
176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
399 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/
DTargetParser.cpp568 static StringRef getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
569 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
582 .Default(FPU); in getFPUSynonym()
670 unsigned llvm::ARM::parseFPU(StringRef FPU) { in parseFPU() argument
671 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
883 unsigned llvm::AArch64::parseFPU(StringRef FPU) { in parseFPU() argument
884 return ARM::parseFPU(FPU); in parseFPU()
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DTargetParser.h134 unsigned parseFPU(StringRef FPU);
197 unsigned parseFPU(StringRef FPU);
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dnew-value-check.s14 # CHECK-STRICT: :18:3: note: FPU instructions cannot be new-value producers for jumps
15 # CHECK-RELAXED: :18:3: note: FPU instructions cannot be new-value producers for jumps
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsRegisterInfo.td43 // Mips 32-bit FPU Registers
48 // Mips 64-bit (aliased) FPU Registers
141 /// Mips Single point precision FPU Registers
175 /// Mips Double point precision FPU Registers (aliased
194 /// Mips Double point precision FPU Registers in MFP64 mode.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.td50 // Mips 32-bit FPU Registers
53 // Mips 64-bit (aliased) FPU Registers
155 /// Mips Single point precision FPU Registers
163 /// Mips Double point precision FPU Registers (aliased
170 /// Mips Double point precision FPU Registers in MFP64 mode.
176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
412 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Ddirective-fpu-diagnostics.s8 @ CHECK: error: Unknown FPU name

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