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Searched refs:MIa (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp345 bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair() argument
347 unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA); in isOrderedCompoundPair()
351 unsigned Opca = MIa.getOpcode(); in isOrderedCompoundPair()
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
DHexagonMCDuplexInfo.cpp572 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair() argument
584 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa), in isOrderedDuplexPair()
593 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa); in isOrderedDuplexPair()
615 if (subInstWouldBeExtended(MIa)) in isOrderedDuplexPair()
645 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair() argument
646 unsigned MIaG = getDuplexCandidateGroup(MIa), in isDuplexPair()
DHexagonMCInstrInfo.h201 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
237 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp336 static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair() argument
338 unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA); in isOrderedCompoundPair()
342 unsigned Opca = MIa.getOpcode(); in isOrderedCompoundPair()
347 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
DHexagonMCDuplexInfo.cpp574 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair() argument
587 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa), in isOrderedDuplexPair()
596 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa); in isOrderedDuplexPair()
618 if (subInstWouldBeExtended(MIa)) in isOrderedDuplexPair()
653 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair() argument
654 unsigned MIaG = getDuplexCandidateGroup(MIa), in isDuplexPair()
DHexagonMCInstrInfo.h225 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
259 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp89 bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
92 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
95 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
96 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
108 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
DLanaiInstrInfo.h38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp90 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis * /*AA*/) const { in areMemAccessesTriviallyDisjoint() argument
91 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
94 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
95 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
107 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
DLanaiInstrInfo.h39 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1341 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr &MIa, in checkInstOffsetsDoNotOverlap() argument
1346 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && in checkInstOffsetsDoNotOverlap()
1349 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
1353 unsigned Width0 = (*MIa.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
1364 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
1367 assert((MIa.mayLoad() || MIa.mayStore()) && in areMemAccessesTriviallyDisjoint()
1372 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
1376 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1384 if (isDS(MIa)) { in areMemAccessesTriviallyDisjoint()
1386 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
[all …]
DSIInstrInfo.h84 bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
167 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
302 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2118 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr &MIa, in checkInstOffsetsDoNotOverlap() argument
2123 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && in checkInstOffsetsDoNotOverlap()
2126 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
2130 unsigned Width0 = (*MIa.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
2141 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
2144 assert((MIa.mayLoad() || MIa.mayStore()) && in areMemAccessesTriviallyDisjoint()
2149 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
2153 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
2156 if (AA && MIa.hasOneMemOperand() && MIb.hasOneMemOperand()) { in areMemAccessesTriviallyDisjoint()
2157 const MachineMemOperand *MMOa = *MIa.memoperands_begin(); in areMemAccessesTriviallyDisjoint()
[all …]
DSIInstrInfo.h118 bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
282 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1427 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1429 assert((MIa.mayLoad() || MIa.mayStore()) &&
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h299 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
365 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
DHexagonInstrInfo.cpp1816 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint() argument
1817 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1818 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1823 if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
1828 if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA)) in areMemAccessesTriviallyDisjoint()
1830 const MachineOperand &BaseA = MIa.getOperand(BasePosA); in areMemAccessesTriviallyDisjoint()
1846 unsigned SizeA = getMemAccessSize(MIa); in areMemAccessesTriviallyDisjoint()
1850 const MachineOperand &OffA = MIa.getOperand(OffsetPosA); in areMemAccessesTriviallyDisjoint()
1852 if (!MIa.getOperand(OffsetPosA).isImm() || in areMemAccessesTriviallyDisjoint()
1855 int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm(); in areMemAccessesTriviallyDisjoint()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp1019 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias() argument
1022 if (!MIa.mayStore() && !MIb.mayStore()) in mayAlias()
1026 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore()) in mayAlias()
1029 return MIa.mayAlias(AA, MIb, /*UseTBAA*/false); in mayAlias()
1032 static bool mayAlias(MachineInstr &MIa, in mayAlias() argument
1036 if (mayAlias(MIa, *MIb, AA)) in mayAlias()
DAArch64InstrInfo.h57 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp563 const DataLayout &DL, MachineInstr *MIa, in MIsNeedChainEdge() argument
565 const MachineFunction *MF = MIa->getParent()->getParent(); in MIsNeedChainEdge()
568 assert ((MIa->mayStore() || MIb->mayStore()) && in MIsNeedChainEdge()
572 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA)) in MIsNeedChainEdge()
580 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) in MIsNeedChainEdge()
583 MachineMemOperand *MMOa = *MIa->memoperands_begin(); in MIsNeedChainEdge()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h1527 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1529 assert((MIa.mayLoad() || MIa.mayStore()) &&
/external/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp1075 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias() argument
1078 if (!MIa.mayStore() && !MIb.mayStore()) in mayAlias()
1082 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore()) in mayAlias()
1085 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
1088 static bool mayAlias(MachineInstr &MIa, in mayAlias() argument
1092 if (mayAlias(MIa, *MIb, TII)) in mayAlias()
DAArch64InstrInfo.h50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.h320 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,

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