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Searched refs:MM3 (Results 1 – 25 of 37) sorted by relevance

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/external/mesa3d/src/mesa/x86/
D3dnow_xform3.S84 MOVQ ( MM0, MM3 ) /* x0 | x0 */
96 PFMUL ( REGOFF(8, ECX), MM3 ) /* x0*m3 | x0*m2 */
102 PFADD ( MM3, MM4 ) /* x0*m3+x1*m7 | x0*m2+x1*m6 */
156 MOVD ( REGOFF(56, ECX), MM3 ) /* | m32 */
181 PFADD ( MM3, MM6 ) /* | x2*m22+m32 */
250 MOVQ ( MM0, MM3 ) /* x1 | x0 */
253 PUNPCKHDQ ( MM3, MM3 ) /* x1 | x1 */
256 PFMUL ( REGOFF(16, ECX), MM3 ) /* x1*m5 | x1*m4 */
259 PFADD ( MM2, MM3 ) /* x0*m1+x1*m5 | x0*m0+x1*m4 */
262 PFADD ( REGOFF(48, ECX), MM3 ) /* x0*m1+...+m11 | x0*m0+x1*m4+m12 */
[all …]
D3dnow_xform4.S85 MOVQ ( MM2, MM3 ) /* x1 | x1 */
93 PFMUL ( REGOFF(24, ECX), MM3 ) /* x1*m7 | x1*m6 */
103 PFADD ( MM1, MM3 )
111 PFADD ( MM3, MM7 )
174 MOVD ( REGOFF(8, EAX), MM3 ) /* | x2 */
186 PFSUBR ( MM7, MM3 ) /* | -x2 */
191 PFACC ( MM3, MM6 ) /* -x2 | x2*m22+x3*m32 */
248 MOVQ ( REGOFF(8, EAX), MM3 ) /* x3 | x2 */
251 MOVQ ( MM3, MM4 ) /* x3 | x2 */
260 PUNPCKLDQ ( MM3, MM3 ) /* x2 | x2 */
[all …]
Dmmx_blend.S276 GMB_ALPHA( MM1, MM3, MM4, MM6 ) ;\
277 GMB_LERP_GSC( MM1, MM2, MM3, MM4, MM5, MM6 ) ;\
278 GMB_PACK( MM3, MM6 ) ;\
279 GMB_STORE( rgba, MM3 )
326 MOVQ ( MM1, MM3 ) ;\
328 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
330 PCMPGTB ( MM3, MM4 ) /* q > p ? 0xff : 0x00 */ ;\
358 MOVQ ( MM1, MM3 ) ;\
360 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
362 PCMPGTB ( MM3, MM4 ) /* q > p ? 0xff : 0x00 */ ;\
D3dnow_xform1.S66 MOVQ ( REGOFF(56, ECX), MM3 ) /* m33 | m32 */
80 PFADD ( MM3, MM5 ) /* x0*m03+m33 | x0*m02+m32 */
178 MOVD ( REGOFF(56, ECX), MM3 ) /* | m32 */
189 MOVD ( MM3, REGOFF(8, EDX) ) /* write r2 */
234 MOVD ( REGOFF(56, ECX), MM3 ) /* | m32 */
243 MOVQ ( MM3, REGOFF(8, EDX) ) /* write r2 (=m32), r3 (=0) */
401 MOVD ( REGOFF(56, ECX), MM3 ) /* | m32 */
415 PFADD ( MM3, MM5 ) /* | x0*m02+m32 */
D3dnow_xform2.S71 MOVD ( REGOFF(12, ECX), MM3 ) /* | m03 */
72 PUNPCKLDQ ( REGOFF(28, ECX), MM3 ) /* m13 | m03 */
95 PFMUL ( MM3, MM7 ) /* x1*m13 | x0*m03 */
146 MOVD ( REGOFF(56, ECX), MM3 ) /* | m32 */
155 MOVQ ( MM3, REGOFF(8, EDX) ) /* write r2 (=m32), r3 (=0) */
280 MOVD ( REGOFF(56, ECX), MM3 ) /* | m32 */
291 MOVD ( MM3, REGOFF(8, EDX) ) /* write r2 */
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td142 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
181 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
217 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
249 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
282 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
DX86GenRegisterInfo.inc87 MM3 = 68,
316 const unsigned MM3_Overlaps[] = { X86::MM3, 0 };
633 { "MM3", MM3_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
920 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
1184 RI->mapDwarfRegToLLVMReg(44, X86::MM3, false );
1244 RI->mapDwarfRegToLLVMReg(32, X86::MM3, false );
1279 RI->mapDwarfRegToLLVMReg(32, X86::MM3, false );
1310 RI->mapDwarfRegToLLVMReg(44, X86::MM3, true );
1370 RI->mapDwarfRegToLLVMReg(32, X86::MM3, true );
1405 RI->mapDwarfRegToLLVMReg(32, X86::MM3, true );
[all …]
DX86RegisterInfo.td150 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
DX86InstrCompiler.td303 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
317 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …4 DR15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h200 ENTRY(MM3) \
/external/capstone/arch/X86/
DX86DisassemblerDecoder.h223 ENTRY(MM3) \
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h210 ENTRY(MM3) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h210 ENTRY(MM3) \
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc140 MM3 = 120,
1178 { X86::MM3 },
1812 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2325 { 44U, X86::MM3 },
2386 { 32U, X86::MM3 },
2431 { 32U, X86::MM3 },
2492 { 44U, X86::MM3 },
2553 { 32U, X86::MM3 },
2598 { 32U, X86::MM3 },
2644 { X86::MM3, 44U },
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp189 case X86::YMM3: case X86::YMM11: case X86::MM3: in getX86RegNum()
/external/ImageMagick/PerlMagick/t/reference/write/composite/
DCopyBlue.miff41 …�MM<�MM@�MM?�MM=�MM<�MM<�MM1�MM/�MM,�MM.�MM/�MM0�MM3�MM4�MM1�MM-�MM-�MM-�MM.�MM0�MM-�MM'�MM�MM4�M…
/external/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst543 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst623 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td155 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
DX86InstrCompiler.td456 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td194 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
DX86InstrCompiler.td473 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
493 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,

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