Home
last modified time | relevance | path

Searched refs:MM4 (Results 1 – 25 of 37) sorted by relevance

12

/external/mesa3d/src/mesa/x86/
D3dnow_xform1.S71 MOVD ( REGIND(EAX), MM4 ) /* | x0 */
72 PUNPCKLDQ ( MM4, MM4 ) /* x0 | x0 */
74 MOVQ ( MM4, MM5 ) /* x0 | x0 */
75 PFMUL ( MM0, MM4 ) /* x0*m01 | x0*m00 */
78 PFADD ( MM2, MM4 ) /* x0*m01+m31 | x0*m00+m30 */
81 MOVQ ( MM4, REGIND(EDX) ) /* write r1, r0 */
183 MOVD ( REGIND(EAX), MM4 ) /* | x0 */
184 PFMUL ( MM0, MM4 ) /* | x0*m00 */
186 PFADD ( MM2, MM4 ) /* m31 | x0*m00+m30 */
187 MOVQ ( MM4, REGIND(EDX) ) /* write r1, r0 */
[all …]
D3dnow_xform4.S70 MOVQ ( REGOFF(8, EAX), MM4 ) /* x3 | x2 */
76 MOVQ ( MM4, MM6 ) /* x3 | x2 */
88 PUNPCKLDQ ( MM4, MM4 ) /* x2 | x2 */
91 MOVQ ( MM4, MM5 ) /* x2 | x2 */
96 PFMUL ( REGOFF(32, ECX), MM4 ) /* x2*m9 | x2*m8 */
106 PFADD ( MM4, MM6 )
172 MOVQ ( REGIND(EAX), MM4 ) /* x1 | x0 */
180 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
189 PFADD ( MM4, MM5 ) /* x1*m11+x2*m21 | x0*m00+x2*m20 */
251 MOVQ ( MM3, MM4 ) /* x3 | x2 */
[all …]
Dmmx_blend.S275 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
276 GMB_ALPHA( MM1, MM3, MM4, MM6 ) ;\
277 GMB_LERP_GSC( MM1, MM2, MM3, MM4, MM5, MM6 ) ;\
327 MOVQ ( MM2, MM4 ) ;\
329 PXOR ( MM7, MM4 ) /* unsigned -> signed */ ;\
330 PCMPGTB ( MM3, MM4 ) /* q > p ? 0xff : 0x00 */ ;\
331 PAND ( MM4, MM1 ) /* q > p ? p : 0 */ ;\
332 PANDN ( MM2, MM4 ) /* q > p ? 0 : q */ ;\
333 POR ( MM1, MM4 ) /* q > p ? p : q */ ;\
334 GMB_STORE( rgba, MM4 )
[all …]
D3dnow_xform2.S74 MOVQ ( REGOFF(48, ECX), MM4 ) /* m31 | m30 */
87 PFADD ( MM4, MM6 ) /* x0*...*m11+m31 | x0*...*m10+m30 */
151 MOVQ ( REGIND(EAX), MM4 ) /* x1 | x0 */
152 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
154 MOVQ ( MM4, REGIND(EDX) ) /* write r1, r0 */
208 MOVQ ( REGOFF(48, ECX), MM4 ) /* m31 | m30 */
221 PFADD ( MM4, MM6 ) /* x0*...*m11+m31 | x0*...*m10+m30 */
285 MOVQ ( REGIND(EAX), MM4 ) /* x1 | x0 */
286 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
288 PFADD ( MM2, MM4 ) /* x1*m11+m31 | x0*m00+m30 */
[all …]
D3dnow_xform3.S87 MOVQ ( MM1, MM4 ) /* x1 | x1 */
99 PFMUL ( REGOFF(24, ECX), MM4 ) /* x1*m7 | x1*m6 */
102 PFADD ( MM3, MM4 ) /* x0*m3+x1*m7 | x0*m2+x1*m6 */
105 PFADD ( MM4, MM5 ) /* r3 | r2 */
164 MOVQ ( REGIND(EAX), MM4 ) /* x1 | x0 */
172 PFMUL ( MM0, MM4 ) /* x1*m11 | x0*m00 */
182 PFADD ( MM4, MM5 ) /* x1*m11+x2*m21 | x0*m00+x2*m20 */
255 MOVQ ( MM1, MM4 ) /* | x2 */
258 PUNPCKLDQ ( MM4, MM4 ) /* x2 | x2 */
261 PFMUL ( REGOFF(32, ECX), MM4 ) /* x2*m9 | x2*m8 */
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td142 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
181 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
217 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
249 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
282 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
DX86GenRegisterInfo.inc88 MM4 = 69,
317 const unsigned MM4_Overlaps[] = { X86::MM4, 0 };
634 { "MM4", MM4_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
920 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
1185 RI->mapDwarfRegToLLVMReg(45, X86::MM4, false );
1245 RI->mapDwarfRegToLLVMReg(33, X86::MM4, false );
1280 RI->mapDwarfRegToLLVMReg(33, X86::MM4, false );
1311 RI->mapDwarfRegToLLVMReg(45, X86::MM4, true );
1371 RI->mapDwarfRegToLLVMReg(33, X86::MM4, true );
1406 RI->mapDwarfRegToLLVMReg(33, X86::MM4, true );
[all …]
DX86RegisterInfo.td151 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
DX86InstrCompiler.td303 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
317 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h201 ENTRY(MM4) \
/external/capstone/arch/X86/
DX86DisassemblerDecoder.h224 ENTRY(MM4) \
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h211 ENTRY(MM4) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h211 ENTRY(MM4) \
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc141 MM4 = 121,
1179 { X86::MM4 },
1812 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2326 { 45U, X86::MM4 },
2387 { 33U, X86::MM4 },
2432 { 33U, X86::MM4 },
2493 { 45U, X86::MM4 },
2554 { 33U, X86::MM4 },
2599 { 33U, X86::MM4 },
2645 { X86::MM4, 45U },
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp192 case X86::YMM4: case X86::YMM12: case X86::MM4: in getX86RegNum()
/external/ImageMagick/PerlMagick/t/reference/write/composite/
DCopyBlue.miff41 …M:�MM<�MM@�MM?�MM=�MM<�MM<�MM1�MM/�MM,�MM.�MM/�MM0�MM3�MM4�MM1�MM-�MM-�MM-�MM.�MM0�MM-�MM'�MM�MM4…
/external/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst543 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst623 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td156 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
DX86InstrCompiler.td456 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td195 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
DX86InstrCompiler.td473 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
493 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,

12