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Searched refs:MM7 (Results 1 – 25 of 36) sorted by relevance

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/external/mesa3d/src/mesa/x86/
D3dnow_xform4.S97 MOVQ ( MM6, MM7 ) /* x3 | x3 */
105 PFMUL ( REGOFF(56, ECX), MM7 ) /* x3*m15 | x3*m14 */
108 PFADD ( MM5, MM7 )
111 PFADD ( MM3, MM7 )
114 MOVQ ( MM7, REGOFF(-8, EDX) )
165 PXOR ( MM7, MM7 ) /* 0 | 0 */
186 PFSUBR ( MM7, MM3 ) /* | -x2 */
238 MOVD ( REGOFF(40, ECX), MM7 ) /* | m10 */
239 PUNPCKLDQ ( REGOFF(56, ECX), MM7 ) /* m14 | m10 */
274 PFMUL ( MM7, MM5 ) /* x3*m14 | x2*m10 */
[all …]
D3dnow_xform2.S81 MOVQ ( MM6, MM7 ) /* x1 | x0 */
84 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
86 PFACC ( MM7, MM6 ) /* x0*m01+x1*m11 | x0*x00+x1*m10 */
92 MOVQ ( MM6, MM7 ) /* x1 | x0 */
95 PFMUL ( MM3, MM7 ) /* x1*m13 | x0*m03 */
98 PFACC ( MM7, MM6 ) /* x0*m03+x1*m13 | x0*x02+x1*m12 */
215 MOVQ ( MM6, MM7 ) /* x1 | x0 */
218 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
220 PFACC ( MM7, MM6 ) /* x0*m01+x1*m11 | x0*x00+x1*m10 */
226 MOVQ ( MM6, MM7 ) /* x1 | x0 */
[all …]
Dmmx_blend.S321 MOVQ ( REGIND(ESP), MM7 ) ;\
328 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
329 PXOR ( MM7, MM4 ) /* unsigned -> signed */ ;\
353 MOVQ ( REGIND(ESP), MM7 ) ;\
360 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
361 PXOR ( MM7, MM4 ) /* unsigned -> signed */ ;\
386 MOVQ ( REGIND(ESP), MM7 ) ;\
392 GMB_MULT_GSR( MM1, MM2, MM4, MM5, MM7 ) ;\
D3dnow_xform3.S169 PXOR ( MM7, MM7 ) /* 0 | 0 */
173 PFSUB ( MM5, MM7 ) /* | -x2 */
187 MOVD ( MM7, REGOFF(-4, EDX) ) /* write r3 */
231 MOVD ( REGOFF(8, ECX), MM7 ) /* | m2 */
232 PUNPCKLDQ ( REGOFF(24, ECX), MM7 ) /* m6 | m2 */
264 PFMUL ( MM7, MM0 ) /* x1*m6 | x0*m2 */
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td142 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
181 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
217 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
249 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
282 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
DX86GenRegisterInfo.inc91 MM7 = 72,
320 const unsigned MM7_Overlaps[] = { X86::MM7, 0 };
637 { "MM7", MM7_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
920 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
1188 RI->mapDwarfRegToLLVMReg(48, X86::MM7, false );
1248 RI->mapDwarfRegToLLVMReg(36, X86::MM7, false );
1283 RI->mapDwarfRegToLLVMReg(36, X86::MM7, false );
1314 RI->mapDwarfRegToLLVMReg(48, X86::MM7, true );
1374 RI->mapDwarfRegToLLVMReg(36, X86::MM7, true );
1409 RI->mapDwarfRegToLLVMReg(36, X86::MM7, true );
[all …]
DX86RegisterInfo.td154 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
DX86InstrCompiler.td303 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
317 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …P2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0 ST1 ST2 ST3…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h204 ENTRY(MM7)
/external/capstone/arch/X86/
DX86DisassemblerDecoder.h227 ENTRY(MM7)
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h214 ENTRY(MM7)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h214 ENTRY(MM7)
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc144 MM7 = 124,
1182 { X86::MM7 },
1812 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2329 { 48U, X86::MM7 },
2390 { 36U, X86::MM7 },
2435 { 36U, X86::MM7 },
2496 { 48U, X86::MM7 },
2557 { 36U, X86::MM7 },
2602 { 36U, X86::MM7 },
2648 { X86::MM7, 48U },
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp201 case X86::YMM7: case X86::YMM15: case X86::MM7: in getX86RegNum()
/external/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst543 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst623 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td159 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
DX86InstrCompiler.td456 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp168 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td198 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
DX86InstrCompiler.td473 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
493 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp210 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()

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