| /external/vixl/test/test-trace-reference/ |
| D | log-sysregs | 1 # NZCV: N:0 Z:0 C:0 V:0
2 # NZCV: N:0 Z:0 C:0 V:0
3 # NZCV: N:0 Z:0 C:0 V:0
4 # NZCV: N:0 Z:0 C:0 V:0
5 # NZCV: N:0 Z:0 C:0 V:0
6 # NZCV: N:0 Z:1 C:0 V:0
7 # NZCV: N:0 Z:1 C:0 V:0
8 # NZCV: N:0 Z:0 C:0 V:0
9 # NZCV: N:0 Z:0 C:0 V:0
10 # NZCV: N:0 Z:0 C:0 V:0
[all …]
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| D | log-state | 67 # NZCV: N:0 Z:0 C:0 V:0
69 # NZCV: N:0 Z:0 C:0 V:0
73 # NZCV: N:0 Z:0 C:0 V:0
75 # NZCV: N:0 Z:0 C:0 V:0
79 # NZCV: N:0 Z:0 C:0 V:0
81 # NZCV: N:0 Z:1 C:0 V:0
91 # NZCV: N:0 Z:1 C:0 V:0
93 # NZCV: N:0 Z:0 C:0 V:0
95 # NZCV: N:0 Z:0 C:0 V:0
96 # NZCV: N:0 Z:0 C:0 V:0
[all …]
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| D | log-all | 70 # NZCV: N:0 Z:0 C:0 V:0
73 # NZCV: N:0 Z:0 C:0 V:0
80 # NZCV: N:0 Z:0 C:0 V:0
83 # NZCV: N:0 Z:0 C:0 V:0
90 # NZCV: N:0 Z:0 C:0 V:0
93 # NZCV: N:0 Z:1 C:0 V:0
112 # NZCV: N:0 Z:1 C:0 V:0
115 # NZCV: N:0 Z:0 C:0 V:0
118 # NZCV: N:0 Z:0 C:0 V:0
120 # NZCV: N:0 Z:0 C:0 V:0
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CondBrTuning.cpp | 95 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
200 if (I->modifiesRegister(AArch64::NZCV, TRI) || in tryToTuneBranch()
201 I->readsRegister(AArch64::NZCV, TRI)) in tryToTuneBranch()
259 if (I->modifiesRegister(AArch64::NZCV, TRI) || in tryToTuneBranch()
260 I->readsRegister(AArch64::NZCV, TRI)) in tryToTuneBranch()
|
| D | AArch64ConditionalCompares.cpp | 304 if (!I->readsRegister(AArch64::NZCV)) { in findConvertibleCompare()
356 MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI); in findConvertibleCompare()
428 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) { in canSpeculateInstrs()
689 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC); in convert() local
702 MIB.addImm(NZCV).addImm(HeadCmpBBCC); in convert()
|
| D | AArch64RegisterBanks.td | 19 /// Conditional register: NZCV.
|
| D | AArch64ConditionOptimizer.cpp | 157 if (SuccBB->isLiveIn(AArch64::NZCV)) in findSuitableCompare()
165 if (I->readsRegister(AArch64::NZCV)) in findSuitableCompare()
|
| D | AArch64InstrInfo.cpp | 434 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
462 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
1290 Instr.modifiesRegister(AArch64::NZCV, TRI)) || in areCFlagsAccessedBetweenInstrs()
1291 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI))) in areCFlagsAccessedBetweenInstrs()
1315 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
1402 if (BB->isLiveIn(AArch64::NZCV)) in areCFlagsAliveInSuccessors()
1437 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); in findCondCodeUsedByInstr()
1452 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); in findCondCodeUsedByInstr()
1549 if (Instr.readsRegister(AArch64::NZCV, TRI)) { in canInstrSubstituteCmpInstr()
1556 if (Instr.modifiesRegister(AArch64::NZCV, TRI)) in canInstrSubstituteCmpInstr()
[all …]
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| D | AArch64InstrFormats.td | 1158 // FIXME: Some of these def NZCV, others don't. Best way to model that?
1176 let Defs = [NZCV] in
1204 let Defs = [NZCV] in
1406 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
1410 let Uses = [NZCV];
1644 let Uses = [NZCV];
1672 let Uses = [NZCV];
1687 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1692 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1693 (implicit NZCV)]> {
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | nzcv-save.ll | 3 ; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV
4 ; CHECK: msr NZCV, [[NZCV_SAVE]]
|
| D | regress-f128csel-flags.ll | 3 ; We used to not mark NZCV as being used in the continuation basic-block
21 ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
|
| D | arm64-regress-f128csel-flags.ll | 3 ; We used to not mark NZCV as being used in the continuation basic-block
21 ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
|
| D | regress-fp128-livein.ll | 3 ; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB,
|
| D | flags-multiuse.ll | 29 ; acceptable, but assuming the call preserves NZCV is not.
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | nzcv-save.ll | 3 ; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV
4 ; CHECK: msr NZCV, [[NZCV_SAVE]]
|
| D | regress-f128csel-flags.ll | 3 ; We used to not mark NZCV as being used in the continuation basic-block
21 ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
|
| D | arm64-regress-f128csel-flags.ll | 3 ; We used to not mark NZCV as being used in the continuation basic-block
21 ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
|
| D | regress-fp128-livein.ll | 3 ; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB,
|
| D | flags-multiuse.ll | 26 ; acceptable, but assuming the call preserves NZCV is not.
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ConditionalCompares.cpp | 300 if (!I->readsRegister(AArch64::NZCV)) { in findConvertibleCompare()
351 MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI); in findConvertibleCompare()
422 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) { in canSpeculateInstrs()
646 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC); in convert() local
660 MIB.addImm(NZCV).addImm(HeadCmpBBCC); in convert()
|
| D | AArch64InstrInfo.cpp | 316 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
343 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
866 if ( ((AccessToCheck & AK_Write) && Instr.modifiesRegister(AArch64::NZCV, TRI)) || in areCFlagsAccessedBetweenInstrs()
867 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI))) in areCFlagsAccessedBetweenInstrs()
889 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
962 if (BB->isLiveIn(AArch64::NZCV)) in areCFlagsAliveInSuccessors()
991 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); in findCondCodeUsedByInstr()
1006 int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); in findCondCodeUsedByInstr()
1100 if (Instr.readsRegister(AArch64::NZCV, TRI)) { in canInstrSubstituteCmpInstr()
1107 if (Instr.modifiesRegister(AArch64::NZCV, TRI)) in canInstrSubstituteCmpInstr()
[all …]
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| D | AArch64ConditionOptimizer.cpp | 148 if (SuccBB->isLiveIn(AArch64::NZCV)) in findSuitableCompare()
156 if (I->readsRegister(AArch64::NZCV)) in findSuitableCompare()
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| D | AArch64InstrFormats.td | 936 // FIXME: Some of these def NZCV, others don't. Best way to model that?
954 let Defs = [NZCV] in
982 let Defs = [NZCV] in
1110 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
1114 let Uses = [NZCV];
1314 let Uses = [NZCV];
1329 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1334 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1335 (implicit NZCV)]> {
1336 let Defs = [NZCV];
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | shift-i64.ll | 23 ; NZCV.
|
| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 8883 __ Msr(NZCV, x10); in AdcsSbcsHelper()
9653 __ Mrs(x0, NZCV); in TEST()
9656 __ Mrs(x1, NZCV); in TEST()
9659 __ Mrs(x2, NZCV); in TEST()
9662 __ Mrs(x3, NZCV); in TEST()
9665 __ Mrs(x4, NZCV); in TEST()
9668 __ Mrs(x5, NZCV); in TEST()
9671 __ Mrs(x6, NZCV); in TEST()
9674 __ Mrs(x7, NZCV); in TEST()
9705 __ Mrs(x0, NZCV); in TEST()
[all …]
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