| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | RuntimeLibcalls.h | 256 O_F32, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMLegalizerInfo.cpp | 210 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; in setFCmpLibcallsAEABI()
261 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}}; in setFCmpLibcallsGNU()
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| D | ARMISelLowering.cpp | 270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ }, in ARMTargetLowering()
362 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, in ARMTargetLowering()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | RuntimeLibcalls.h | 326 O_F32, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/WebAssembly/ |
| D | libcalls.ll | 62 ; fcmp ord and unord (RTLIB::O_F32 / RTLIB::UO_F32 etc) are a special case (see
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelLowering.cpp | 261 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2"); in setMips16HardFloatLibCalls()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips16ISelLowering.cpp | 261 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2"); in setMips16HardFloatLibCalls()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | RuntimeLibcalls.def | 362 HANDLE_LIBCALL(O_F32, "__unordsf2")
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 348 Names[RTLIB::O_F32] = "__unordsf2"; in InitLibcallNames()
791 CCs[RTLIB::O_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRuntimeLibcallSignatures.cpp | 305 Table[RTLIB::O_F32] = unsupported; in RuntimeLibcallSignatureTable()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 525 CCs[RTLIB::O_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 288 Names[RTLIB::O_F32] = "__unordsf2"; in InitLibcallNames()
539 CCs[RTLIB::O_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
|
| D | LegalizeFloatTypes.cpp | 651 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; in SoftenSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); in ARMTargetLowering()
216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); in ARMTargetLowering()
332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); in ARMTargetLowering()
333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); in ARMTargetLowering()
341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); in ARMTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1683 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2"); in HexagonTargetLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 203 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : in softenSetCCOperands()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 2181 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2"); in HexagonTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 208 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : in softenSetCCOperands()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 199 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ }, in ARMTargetLowering()
298 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ }, in ARMTargetLowering()
|