/external/llvm/lib/Target/Mips/ |
D | Mips64r6InstrInfo.td | 178 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), 181 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), 187 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), 190 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
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D | MipsCondMov.td | 74 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; 77 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
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D | Mips32r6InstrInfo.td | 922 (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))), 923 (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>; 925 (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))), 926 (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;
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D | MipsInstrInfo.td | 1023 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 2578 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 2580 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | Mips64r6InstrInfo.td | 229 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), 232 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), 238 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), 241 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
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D | MipsCondMov.td | 74 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; 77 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
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D | Mips32r6InstrInfo.td | 1062 (OROp (SELEQZOp RC:$t, (SLTiOp RC:$cond, (Plus1 imm:$imm))), 1063 (SELNEZOp RC:$f, (SLTiOp RC:$cond, (Plus1 imm:$imm))))>; 1065 (OROp (SELEQZOp RC:$t, (SLTiuOp RC:$cond, (Plus1 imm:$imm))), 1066 (SELNEZOp RC:$f, (SLTiuOp RC:$cond, (Plus1 imm:$imm))))>;
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D | MicroMips32r6InstrInfo.td | 1790 (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>, 1793 (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
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D | MipsInstrInfo.td | 1250 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 3157 (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; 3159 (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
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/external/google-breakpad/src/testing/test/ |
D | gmock-generated-actions_test.cc | 82 const char* Plus1(const char* s) { return s + 1; } in Plus1() function 964 ACTION_P(Plus1, x) { return x; } in ACTION_P() argument 975 Action<int()> a = Plus1<int&>(x); in TEST()
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D | gmock-more-actions_test.cc | 93 const char* Plus1(const char* s) { return s + 1; } in Plus1() function
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D | gmock-actions_test.cc | 1032 const char* Plus1(const char* s) { return s + 1; } in Plus1() function
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/external/googletest/googlemock/test/ |
D | gmock-generated-actions_test.cc | 820 ACTION_P(Plus1, x) { return x; } in ACTION_P() argument 831 Action<int()> a = Plus1<int&>(x); in TEST()
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D | gmock-more-actions_test.cc | 87 const char* Plus1(const char* s) { return s + 1; } in Plus1() function
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
D | MipsGenDAGISel.inc | 2091 /* 3673*/ OPC_EmitNodeXForm, 2, 4, // Plus1 2098 …// Dst: (BEQ (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs))… 2111 /* 3713*/ OPC_EmitNodeXForm, 2, 4, // Plus1 2118 …// Dst: (BEQ (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)… 2179 /* 3841*/ OPC_EmitNodeXForm, 2, 4, // Plus1 2186 …// Dst: (BEQ_MM (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):… 2199 /* 3881*/ OPC_EmitNodeXForm, 2, 4, // Plus1 2206 …// Dst: (BEQ_MM (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] })… 2265 /* 4001*/ OPC_EmitNodeXForm, 2, 4, // Plus1 2271 …// Dst: (BEQZC_MMR6 (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32]… [all …]
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