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Searched refs:QPR (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td623 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
625 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
629 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
633 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1049 : PseudoNLdSt<(outs QPR:$dst),
1050 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1053 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1054 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1100 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1124 def : Pat<(vector_insert (v4f32 QPR:$src),
[all …]
DARMRegisterInfo.td359 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
362 let AltOrders = [(rotl QPR, 8)];
367 // Subset of QPR that have 32-bit SPR subregs.
369 128, (trunc QPR, 8)> {
373 // Subset of QPR that have DPR_8 and SPR_8 subregs.
375 128, (trunc QPR, 4)> {
390 128, (interleave QPR, TuplesOE2D)> {
393 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
422 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
DARMRegisterBanks.td14 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
DA15SDOptimizer.cpp70 bool QPR = false);
421 unsigned Lane, bool QPR) { in createDupLane() argument
422 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : in createDupLane()
425 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out) in createDupLane()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td625 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
627 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
631 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
635 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1026 : PseudoNLdSt<(outs QPR:$dst),
1027 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1030 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1031 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1076 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1100 def : Pat<(vector_insert (v4f32 QPR:$src),
[all …]
DARMRegisterInfo.td313 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
316 let AltOrders = [(rotl QPR, 8)];
320 // Subset of QPR that have 32-bit SPR subregs.
322 128, (trunc QPR, 8)>;
324 // Subset of QPR that have DPR_8 and SPR_8 subregs.
326 128, (trunc QPR, 4)>;
339 128, (interleave QPR, TuplesOE2D)> {
342 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
371 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
DA15SDOptimizer.cpp72 bool QPR = false);
429 unsigned Lane, bool QPR) { in createDupLane() argument
430 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : in createDupLane()
435 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), in createDupLane()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td181 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
183 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
188 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
190 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
195 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
197 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
544 : PseudoNLdSt<(outs QPR:$dst),
545 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
548 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
549 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
[all …]
DARMRegisterInfo.td297 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
301 let AltOrders = [(rotl QPR, 8)];
305 // Subset of QPR that have 32-bit SPR subregs.
307 128, (trunc QPR, 8)> {
312 // Subset of QPR that have DPR_8 and SPR_8 subregs.
314 128, (trunc QPR, 4)> {
323 (QPR qsub_0, qsub_1)];
342 (QPR qsub_0, qsub_1, qsub_2, qsub_3)];
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc1247 …} (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:{ *:[v4…
1248 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
1255 …} (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vd), (and:{ *:[v2i64] } QPR:{ *:[v2…
1256 … // Dst: (VBSLq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vd, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
2017 …QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, (xor:{ *:…
2018 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2044 …QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } QPR:{ *:[v4i3…
2045 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2068 …QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (bitconvert:{…
2069 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
[all …]
DARMGenGlobalISel.inc1593 …R:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i6…
1622 …R:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i6…
1651 …QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1016:{ *:[iPTR] }, …
1680 …QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1017:{ *:[iPTR] }, …
1749 … } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64…
1769 … } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64…
1789 …// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VAD…
1809 …// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VAD…
1825 …// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } …
2031 …R:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i3…
[all …]
DARMGenRegisterInfo.inc1872 // QPR Register Class...
1873 const MCPhysReg QPR[] = {
1877 // QPR Bit set.
2671 { QPR, QPRBits, 1659, 16, sizeof(QPRBits), ARM::QPRRegClassID, 16, 1, true },
3559 { 128, 128, 128, VTLists+20 }, // QPR
9539 { // QPR
9540 37, // dsub_0 -> QPR
9541 37, // dsub_1 -> QPR
13474 {4, 64}, // QPR
DARMGenAsmMatcher.inc4392 MCK_QPR, // register class 'QPR'
/external/clang/test/CodeGenCXX/
Dnested-base-member-access.cpp15 void QPR() { printf("iQ = %d\n", iQ); } in QPR() function
39 this->MPR(); this->PPR(); this->QPR(); in PR()
Dconstructor-init.cpp25 void QPR() {printf("iQ = %d\n", iQ); }; in QPR() function
40 QPR(); in PR()
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc9363 // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)
9374 // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)
9411 // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)
9422 // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)
9474 // (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9487 // (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9526 // (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9539 // (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9565 // (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9604 // (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
[all …]
DARMGenRegisterInfo.inc1508 // QPR Register Class...
1509 static uint16_t QPR[] = {
1513 // QPR Bit set.
2212 { "QPR", QPR, QPRBits, 16, sizeof(QPRBits), ARM_QPRRegClassID, 16, 16, 1, 1 },
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Da15-SD-dep.ll56 ; Test that DPair can be successfully passed as QPR.
Dcoalesce-subregs.ll322 ; once under rare circumstances. When widening a register from QPR to DTriple
Dvldlane.ll519 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
/external/llvm/test/CodeGen/ARM/
Da15-SD-dep.ll60 ; Test that DPair can be successfully passed as QPR.
Dcoalesce-subregs.ll322 ; once under rare circumstances. When widening a register from QPR to DTriple
Dvldlane.ll503 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvldlane.ll491 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart2.csv14072 ,"IT","PKF","Prati","Prati",,"--3-----","RL","9805","QPR",,

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