1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|*Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9/* Capstone Disassembly Engine, http://www.capstone-engine.org */ 10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ 11 12 13#ifdef GET_REGINFO_ENUM 14#undef GET_REGINFO_ENUM 15 16enum { 17 ARM_NoRegister, 18 ARM_APSR = 1, 19 ARM_APSR_NZCV = 2, 20 ARM_CPSR = 3, 21 ARM_FPEXC = 4, 22 ARM_FPINST = 5, 23 ARM_FPSCR = 6, 24 ARM_FPSCR_NZCV = 7, 25 ARM_FPSID = 8, 26 ARM_ITSTATE = 9, 27 ARM_LR = 10, 28 ARM_PC = 11, 29 ARM_SP = 12, 30 ARM_SPSR = 13, 31 ARM_D0 = 14, 32 ARM_D1 = 15, 33 ARM_D2 = 16, 34 ARM_D3 = 17, 35 ARM_D4 = 18, 36 ARM_D5 = 19, 37 ARM_D6 = 20, 38 ARM_D7 = 21, 39 ARM_D8 = 22, 40 ARM_D9 = 23, 41 ARM_D10 = 24, 42 ARM_D11 = 25, 43 ARM_D12 = 26, 44 ARM_D13 = 27, 45 ARM_D14 = 28, 46 ARM_D15 = 29, 47 ARM_D16 = 30, 48 ARM_D17 = 31, 49 ARM_D18 = 32, 50 ARM_D19 = 33, 51 ARM_D20 = 34, 52 ARM_D21 = 35, 53 ARM_D22 = 36, 54 ARM_D23 = 37, 55 ARM_D24 = 38, 56 ARM_D25 = 39, 57 ARM_D26 = 40, 58 ARM_D27 = 41, 59 ARM_D28 = 42, 60 ARM_D29 = 43, 61 ARM_D30 = 44, 62 ARM_D31 = 45, 63 ARM_FPINST2 = 46, 64 ARM_MVFR0 = 47, 65 ARM_MVFR1 = 48, 66 ARM_MVFR2 = 49, 67 ARM_Q0 = 50, 68 ARM_Q1 = 51, 69 ARM_Q2 = 52, 70 ARM_Q3 = 53, 71 ARM_Q4 = 54, 72 ARM_Q5 = 55, 73 ARM_Q6 = 56, 74 ARM_Q7 = 57, 75 ARM_Q8 = 58, 76 ARM_Q9 = 59, 77 ARM_Q10 = 60, 78 ARM_Q11 = 61, 79 ARM_Q12 = 62, 80 ARM_Q13 = 63, 81 ARM_Q14 = 64, 82 ARM_Q15 = 65, 83 ARM_R0 = 66, 84 ARM_R1 = 67, 85 ARM_R2 = 68, 86 ARM_R3 = 69, 87 ARM_R4 = 70, 88 ARM_R5 = 71, 89 ARM_R6 = 72, 90 ARM_R7 = 73, 91 ARM_R8 = 74, 92 ARM_R9 = 75, 93 ARM_R10 = 76, 94 ARM_R11 = 77, 95 ARM_R12 = 78, 96 ARM_S0 = 79, 97 ARM_S1 = 80, 98 ARM_S2 = 81, 99 ARM_S3 = 82, 100 ARM_S4 = 83, 101 ARM_S5 = 84, 102 ARM_S6 = 85, 103 ARM_S7 = 86, 104 ARM_S8 = 87, 105 ARM_S9 = 88, 106 ARM_S10 = 89, 107 ARM_S11 = 90, 108 ARM_S12 = 91, 109 ARM_S13 = 92, 110 ARM_S14 = 93, 111 ARM_S15 = 94, 112 ARM_S16 = 95, 113 ARM_S17 = 96, 114 ARM_S18 = 97, 115 ARM_S19 = 98, 116 ARM_S20 = 99, 117 ARM_S21 = 100, 118 ARM_S22 = 101, 119 ARM_S23 = 102, 120 ARM_S24 = 103, 121 ARM_S25 = 104, 122 ARM_S26 = 105, 123 ARM_S27 = 106, 124 ARM_S28 = 107, 125 ARM_S29 = 108, 126 ARM_S30 = 109, 127 ARM_S31 = 110, 128 ARM_D0_D2 = 111, 129 ARM_D1_D3 = 112, 130 ARM_D2_D4 = 113, 131 ARM_D3_D5 = 114, 132 ARM_D4_D6 = 115, 133 ARM_D5_D7 = 116, 134 ARM_D6_D8 = 117, 135 ARM_D7_D9 = 118, 136 ARM_D8_D10 = 119, 137 ARM_D9_D11 = 120, 138 ARM_D10_D12 = 121, 139 ARM_D11_D13 = 122, 140 ARM_D12_D14 = 123, 141 ARM_D13_D15 = 124, 142 ARM_D14_D16 = 125, 143 ARM_D15_D17 = 126, 144 ARM_D16_D18 = 127, 145 ARM_D17_D19 = 128, 146 ARM_D18_D20 = 129, 147 ARM_D19_D21 = 130, 148 ARM_D20_D22 = 131, 149 ARM_D21_D23 = 132, 150 ARM_D22_D24 = 133, 151 ARM_D23_D25 = 134, 152 ARM_D24_D26 = 135, 153 ARM_D25_D27 = 136, 154 ARM_D26_D28 = 137, 155 ARM_D27_D29 = 138, 156 ARM_D28_D30 = 139, 157 ARM_D29_D31 = 140, 158 ARM_Q0_Q1 = 141, 159 ARM_Q1_Q2 = 142, 160 ARM_Q2_Q3 = 143, 161 ARM_Q3_Q4 = 144, 162 ARM_Q4_Q5 = 145, 163 ARM_Q5_Q6 = 146, 164 ARM_Q6_Q7 = 147, 165 ARM_Q7_Q8 = 148, 166 ARM_Q8_Q9 = 149, 167 ARM_Q9_Q10 = 150, 168 ARM_Q10_Q11 = 151, 169 ARM_Q11_Q12 = 152, 170 ARM_Q12_Q13 = 153, 171 ARM_Q13_Q14 = 154, 172 ARM_Q14_Q15 = 155, 173 ARM_Q0_Q1_Q2_Q3 = 156, 174 ARM_Q1_Q2_Q3_Q4 = 157, 175 ARM_Q2_Q3_Q4_Q5 = 158, 176 ARM_Q3_Q4_Q5_Q6 = 159, 177 ARM_Q4_Q5_Q6_Q7 = 160, 178 ARM_Q5_Q6_Q7_Q8 = 161, 179 ARM_Q6_Q7_Q8_Q9 = 162, 180 ARM_Q7_Q8_Q9_Q10 = 163, 181 ARM_Q8_Q9_Q10_Q11 = 164, 182 ARM_Q9_Q10_Q11_Q12 = 165, 183 ARM_Q10_Q11_Q12_Q13 = 166, 184 ARM_Q11_Q12_Q13_Q14 = 167, 185 ARM_Q12_Q13_Q14_Q15 = 168, 186 ARM_R12_SP = 169, 187 ARM_R0_R1 = 170, 188 ARM_R2_R3 = 171, 189 ARM_R4_R5 = 172, 190 ARM_R6_R7 = 173, 191 ARM_R8_R9 = 174, 192 ARM_R10_R11 = 175, 193 ARM_D0_D1_D2 = 176, 194 ARM_D1_D2_D3 = 177, 195 ARM_D2_D3_D4 = 178, 196 ARM_D3_D4_D5 = 179, 197 ARM_D4_D5_D6 = 180, 198 ARM_D5_D6_D7 = 181, 199 ARM_D6_D7_D8 = 182, 200 ARM_D7_D8_D9 = 183, 201 ARM_D8_D9_D10 = 184, 202 ARM_D9_D10_D11 = 185, 203 ARM_D10_D11_D12 = 186, 204 ARM_D11_D12_D13 = 187, 205 ARM_D12_D13_D14 = 188, 206 ARM_D13_D14_D15 = 189, 207 ARM_D14_D15_D16 = 190, 208 ARM_D15_D16_D17 = 191, 209 ARM_D16_D17_D18 = 192, 210 ARM_D17_D18_D19 = 193, 211 ARM_D18_D19_D20 = 194, 212 ARM_D19_D20_D21 = 195, 213 ARM_D20_D21_D22 = 196, 214 ARM_D21_D22_D23 = 197, 215 ARM_D22_D23_D24 = 198, 216 ARM_D23_D24_D25 = 199, 217 ARM_D24_D25_D26 = 200, 218 ARM_D25_D26_D27 = 201, 219 ARM_D26_D27_D28 = 202, 220 ARM_D27_D28_D29 = 203, 221 ARM_D28_D29_D30 = 204, 222 ARM_D29_D30_D31 = 205, 223 ARM_D0_D2_D4 = 206, 224 ARM_D1_D3_D5 = 207, 225 ARM_D2_D4_D6 = 208, 226 ARM_D3_D5_D7 = 209, 227 ARM_D4_D6_D8 = 210, 228 ARM_D5_D7_D9 = 211, 229 ARM_D6_D8_D10 = 212, 230 ARM_D7_D9_D11 = 213, 231 ARM_D8_D10_D12 = 214, 232 ARM_D9_D11_D13 = 215, 233 ARM_D10_D12_D14 = 216, 234 ARM_D11_D13_D15 = 217, 235 ARM_D12_D14_D16 = 218, 236 ARM_D13_D15_D17 = 219, 237 ARM_D14_D16_D18 = 220, 238 ARM_D15_D17_D19 = 221, 239 ARM_D16_D18_D20 = 222, 240 ARM_D17_D19_D21 = 223, 241 ARM_D18_D20_D22 = 224, 242 ARM_D19_D21_D23 = 225, 243 ARM_D20_D22_D24 = 226, 244 ARM_D21_D23_D25 = 227, 245 ARM_D22_D24_D26 = 228, 246 ARM_D23_D25_D27 = 229, 247 ARM_D24_D26_D28 = 230, 248 ARM_D25_D27_D29 = 231, 249 ARM_D26_D28_D30 = 232, 250 ARM_D27_D29_D31 = 233, 251 ARM_D0_D2_D4_D6 = 234, 252 ARM_D1_D3_D5_D7 = 235, 253 ARM_D2_D4_D6_D8 = 236, 254 ARM_D3_D5_D7_D9 = 237, 255 ARM_D4_D6_D8_D10 = 238, 256 ARM_D5_D7_D9_D11 = 239, 257 ARM_D6_D8_D10_D12 = 240, 258 ARM_D7_D9_D11_D13 = 241, 259 ARM_D8_D10_D12_D14 = 242, 260 ARM_D9_D11_D13_D15 = 243, 261 ARM_D10_D12_D14_D16 = 244, 262 ARM_D11_D13_D15_D17 = 245, 263 ARM_D12_D14_D16_D18 = 246, 264 ARM_D13_D15_D17_D19 = 247, 265 ARM_D14_D16_D18_D20 = 248, 266 ARM_D15_D17_D19_D21 = 249, 267 ARM_D16_D18_D20_D22 = 250, 268 ARM_D17_D19_D21_D23 = 251, 269 ARM_D18_D20_D22_D24 = 252, 270 ARM_D19_D21_D23_D25 = 253, 271 ARM_D20_D22_D24_D26 = 254, 272 ARM_D21_D23_D25_D27 = 255, 273 ARM_D22_D24_D26_D28 = 256, 274 ARM_D23_D25_D27_D29 = 257, 275 ARM_D24_D26_D28_D30 = 258, 276 ARM_D25_D27_D29_D31 = 259, 277 ARM_D1_D2 = 260, 278 ARM_D3_D4 = 261, 279 ARM_D5_D6 = 262, 280 ARM_D7_D8 = 263, 281 ARM_D9_D10 = 264, 282 ARM_D11_D12 = 265, 283 ARM_D13_D14 = 266, 284 ARM_D15_D16 = 267, 285 ARM_D17_D18 = 268, 286 ARM_D19_D20 = 269, 287 ARM_D21_D22 = 270, 288 ARM_D23_D24 = 271, 289 ARM_D25_D26 = 272, 290 ARM_D27_D28 = 273, 291 ARM_D29_D30 = 274, 292 ARM_D1_D2_D3_D4 = 275, 293 ARM_D3_D4_D5_D6 = 276, 294 ARM_D5_D6_D7_D8 = 277, 295 ARM_D7_D8_D9_D10 = 278, 296 ARM_D9_D10_D11_D12 = 279, 297 ARM_D11_D12_D13_D14 = 280, 298 ARM_D13_D14_D15_D16 = 281, 299 ARM_D15_D16_D17_D18 = 282, 300 ARM_D17_D18_D19_D20 = 283, 301 ARM_D19_D20_D21_D22 = 284, 302 ARM_D21_D22_D23_D24 = 285, 303 ARM_D23_D24_D25_D26 = 286, 304 ARM_D25_D26_D27_D28 = 287, 305 ARM_D27_D28_D29_D30 = 288, 306 ARM_NUM_TARGET_REGS // 289 307}; 308 309// Register classes 310enum { 311 ARM_SPRRegClassID = 0, 312 ARM_GPRRegClassID = 1, 313 ARM_GPRwithAPSRRegClassID = 2, 314 ARM_SPR_8RegClassID = 3, 315 ARM_GPRnopcRegClassID = 4, 316 ARM_rGPRRegClassID = 5, 317 ARM_hGPRRegClassID = 6, 318 ARM_tGPRRegClassID = 7, 319 ARM_GPRnopc_and_hGPRRegClassID = 8, 320 ARM_hGPR_and_rGPRRegClassID = 9, 321 ARM_tcGPRRegClassID = 10, 322 ARM_tGPR_and_tcGPRRegClassID = 11, 323 ARM_CCRRegClassID = 12, 324 ARM_GPRspRegClassID = 13, 325 ARM_hGPR_and_tcGPRRegClassID = 14, 326 ARM_DPRRegClassID = 15, 327 ARM_DPR_VFP2RegClassID = 16, 328 ARM_DPR_8RegClassID = 17, 329 ARM_GPRPairRegClassID = 18, 330 ARM_GPRPair_with_gsub_1_in_rGPRRegClassID = 19, 331 ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 20, 332 ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 21, 333 ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 22, 334 ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 23, 335 ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 24, 336 ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 25, 337 ARM_DPairSpcRegClassID = 26, 338 ARM_DPairSpc_with_ssub_0RegClassID = 27, 339 ARM_DPairSpc_with_dsub_2_then_ssub_0RegClassID = 28, 340 ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 29, 341 ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 30, 342 ARM_DPairRegClassID = 31, 343 ARM_DPair_with_ssub_0RegClassID = 32, 344 ARM_QPRRegClassID = 33, 345 ARM_DPair_with_ssub_2RegClassID = 34, 346 ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 35, 347 ARM_QPR_VFP2RegClassID = 36, 348 ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 37, 349 ARM_QPR_8RegClassID = 38, 350 ARM_DTripleRegClassID = 39, 351 ARM_DTripleSpcRegClassID = 40, 352 ARM_DTripleSpc_with_ssub_0RegClassID = 41, 353 ARM_DTriple_with_ssub_0RegClassID = 42, 354 ARM_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 43, 355 ARM_DTriple_with_qsub_0_in_QPRRegClassID = 44, 356 ARM_DTriple_with_ssub_2RegClassID = 45, 357 ARM_DTripleSpc_with_dsub_2_then_ssub_0RegClassID = 46, 358 ARM_DTriple_with_dsub_2_then_ssub_0RegClassID = 47, 359 ARM_DTripleSpc_with_dsub_4_then_ssub_0RegClassID = 48, 360 ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 49, 361 ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 50, 362 ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 51, 363 ARM_DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 52, 364 ARM_DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 53, 365 ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 54, 366 ARM_DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID = 55, 367 ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 56, 368 ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 57, 369 ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 58, 370 ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 59, 371 ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 60, 372 ARM_DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID = 61, 373 ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 62, 374 ARM_DQuadSpcRegClassID = 63, 375 ARM_DQuadSpc_with_ssub_0RegClassID = 64, 376 ARM_DQuadSpc_with_dsub_2_then_ssub_0RegClassID = 65, 377 ARM_DQuadSpc_with_dsub_4_then_ssub_0RegClassID = 66, 378 ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 67, 379 ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 68, 380 ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 69, 381 ARM_DQuadRegClassID = 70, 382 ARM_DQuad_with_ssub_0RegClassID = 71, 383 ARM_DQuad_with_ssub_2RegClassID = 72, 384 ARM_QQPRRegClassID = 73, 385 ARM_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 74, 386 ARM_DQuad_with_dsub_2_then_ssub_0RegClassID = 75, 387 ARM_DQuad_with_dsub_3_then_ssub_0RegClassID = 76, 388 ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 77, 389 ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 78, 390 ARM_DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 79, 391 ARM_DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 80, 392 ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 81, 393 ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 82, 394 ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 83, 395 ARM_DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 84, 396 ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 85, 397 ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 86, 398 ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 87, 399 ARM_DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID = 88, 400 ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 89, 401 ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 90, 402 ARM_QQQQPRRegClassID = 91, 403 ARM_QQQQPR_with_ssub_0RegClassID = 92, 404 ARM_QQQQPR_with_dsub_2_then_ssub_0RegClassID = 93, 405 ARM_QQQQPR_with_dsub_5_then_ssub_0RegClassID = 94, 406 ARM_QQQQPR_with_dsub_7_then_ssub_0RegClassID = 95, 407 ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID = 96, 408 ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID = 97, 409 ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID = 98, 410 ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID = 99 411}; 412 413// Subregister indices 414enum { 415 ARM_NoSubRegister, 416 ARM_dsub_0, // 1 417 ARM_dsub_1, // 2 418 ARM_dsub_2, // 3 419 ARM_dsub_3, // 4 420 ARM_dsub_4, // 5 421 ARM_dsub_5, // 6 422 ARM_dsub_6, // 7 423 ARM_dsub_7, // 8 424 ARM_gsub_0, // 9 425 ARM_gsub_1, // 10 426 ARM_qqsub_0, // 11 427 ARM_qqsub_1, // 12 428 ARM_qsub_0, // 13 429 ARM_qsub_1, // 14 430 ARM_qsub_2, // 15 431 ARM_qsub_3, // 16 432 ARM_ssub_0, // 17 433 ARM_ssub_1, // 18 434 ARM_ssub_2, // 19 435 ARM_ssub_3, // 20 436 ARM_dsub_2_then_ssub_0, // 21 437 ARM_dsub_2_then_ssub_1, // 22 438 ARM_dsub_3_then_ssub_0, // 23 439 ARM_dsub_3_then_ssub_1, // 24 440 ARM_dsub_7_then_ssub_0, // 25 441 ARM_dsub_7_then_ssub_1, // 26 442 ARM_dsub_6_then_ssub_0, // 27 443 ARM_dsub_6_then_ssub_1, // 28 444 ARM_dsub_5_then_ssub_0, // 29 445 ARM_dsub_5_then_ssub_1, // 30 446 ARM_dsub_4_then_ssub_0, // 31 447 ARM_dsub_4_then_ssub_1, // 32 448 ARM_dsub_0_dsub_2, // 33 449 ARM_dsub_0_dsub_1_dsub_2, // 34 450 ARM_dsub_1_dsub_3, // 35 451 ARM_dsub_1_dsub_2_dsub_3, // 36 452 ARM_dsub_1_dsub_2, // 37 453 ARM_dsub_0_dsub_2_dsub_4, // 38 454 ARM_dsub_0_dsub_2_dsub_4_dsub_6, // 39 455 ARM_dsub_1_dsub_3_dsub_5, // 40 456 ARM_dsub_1_dsub_3_dsub_5_dsub_7, // 41 457 ARM_dsub_1_dsub_2_dsub_3_dsub_4, // 42 458 ARM_dsub_2_dsub_4, // 43 459 ARM_dsub_2_dsub_3_dsub_4, // 44 460 ARM_dsub_2_dsub_4_dsub_6, // 45 461 ARM_dsub_3_dsub_5, // 46 462 ARM_dsub_3_dsub_4_dsub_5, // 47 463 ARM_dsub_3_dsub_5_dsub_7, // 48 464 ARM_dsub_3_dsub_4, // 49 465 ARM_dsub_3_dsub_4_dsub_5_dsub_6, // 50 466 ARM_dsub_4_dsub_6, // 51 467 ARM_dsub_4_dsub_5_dsub_6, // 52 468 ARM_dsub_5_dsub_7, // 53 469 ARM_dsub_5_dsub_6_dsub_7, // 54 470 ARM_dsub_5_dsub_6, // 55 471 ARM_qsub_1_qsub_2, // 56 472 ARM_NUM_TARGET_SUBREGS 473}; 474 475#endif // GET_REGINFO_ENUM 476 477/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 478|* *| 479|*MC Register Information *| 480|* *| 481|* Automatically generated file, do not edit! *| 482|* *| 483\*===----------------------------------------------------------------------===*/ 484 485/* Capstone Disassembly Engine, http://www.capstone-engine.org */ 486/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ 487 488 489#ifdef GET_REGINFO_MC_DESC 490#undef GET_REGINFO_MC_DESC 491 492static MCPhysReg ARMRegDiffLists[] = { 493 /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 494 /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 495 /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 496 /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 497 /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0, 498 /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0, 499 /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0, 500 /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0, 501 /* 91 */ 40, 1, 1, 1, 1, 1, 0, 502 /* 98 */ 65196, 1, 1, 1, 1, 1, 0, 503 /* 105 */ 40, 1, 1, 1, 1, 0, 504 /* 111 */ 42, 1, 1, 1, 1, 0, 505 /* 117 */ 42, 1, 1, 1, 0, 506 /* 122 */ 64510, 1, 1, 1, 0, 507 /* 127 */ 65015, 1, 1, 1, 0, 508 /* 132 */ 65282, 1, 1, 1, 0, 509 /* 137 */ 65348, 1, 1, 1, 0, 510 /* 142 */ 13, 1, 1, 0, 511 /* 146 */ 42, 1, 1, 0, 512 /* 150 */ 65388, 1, 1, 0, 513 /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0, 514 /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0, 515 /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0, 516 /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0, 517 /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0, 518 /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0, 519 /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0, 520 /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0, 521 /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0, 522 /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0, 523 /* 254 */ 65489, 133, 65416, 1, 1, 0, 524 /* 260 */ 65490, 133, 65416, 1, 1, 0, 525 /* 266 */ 65491, 133, 65416, 1, 1, 0, 526 /* 272 */ 65492, 133, 65416, 1, 1, 0, 527 /* 278 */ 65493, 133, 65416, 1, 1, 0, 528 /* 284 */ 65494, 133, 65416, 1, 1, 0, 529 /* 290 */ 65495, 133, 65416, 1, 1, 0, 530 /* 296 */ 65496, 133, 65416, 1, 1, 0, 531 /* 302 */ 65497, 133, 65416, 1, 1, 0, 532 /* 308 */ 65498, 133, 65416, 1, 1, 0, 533 /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0, 534 /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0, 535 /* 332 */ 65136, 1, 3, 1, 3, 1, 0, 536 /* 339 */ 65326, 1, 3, 1, 0, 537 /* 344 */ 13, 1, 0, 538 /* 347 */ 14, 1, 0, 539 /* 350 */ 65, 1, 0, 540 /* 353 */ 65500, 65, 1, 65471, 66, 1, 0, 541 /* 360 */ 65291, 66, 1, 65470, 67, 1, 0, 542 /* 367 */ 65439, 65, 1, 65472, 67, 1, 0, 543 /* 374 */ 65501, 67, 1, 65469, 68, 1, 0, 544 /* 381 */ 65439, 66, 1, 65471, 68, 1, 0, 545 /* 388 */ 65292, 68, 1, 65468, 69, 1, 0, 546 /* 395 */ 65439, 67, 1, 65470, 69, 1, 0, 547 /* 402 */ 65502, 69, 1, 65467, 70, 1, 0, 548 /* 409 */ 65439, 68, 1, 65469, 70, 1, 0, 549 /* 416 */ 65293, 70, 1, 65466, 71, 1, 0, 550 /* 423 */ 65439, 69, 1, 65468, 71, 1, 0, 551 /* 430 */ 65503, 71, 1, 65465, 72, 1, 0, 552 /* 437 */ 65439, 70, 1, 65467, 72, 1, 0, 553 /* 444 */ 65294, 72, 1, 65464, 73, 1, 0, 554 /* 451 */ 65439, 71, 1, 65466, 73, 1, 0, 555 /* 458 */ 65504, 73, 1, 65463, 74, 1, 0, 556 /* 465 */ 65439, 72, 1, 65465, 74, 1, 0, 557 /* 472 */ 65295, 74, 1, 65462, 75, 1, 0, 558 /* 479 */ 65439, 73, 1, 65464, 75, 1, 0, 559 /* 486 */ 65505, 75, 1, 65461, 76, 1, 0, 560 /* 493 */ 65439, 74, 1, 65463, 76, 1, 0, 561 /* 500 */ 65296, 76, 1, 65460, 77, 1, 0, 562 /* 507 */ 65439, 75, 1, 65462, 77, 1, 0, 563 /* 514 */ 65506, 77, 1, 65459, 78, 1, 0, 564 /* 521 */ 65439, 76, 1, 65461, 78, 1, 0, 565 /* 528 */ 65297, 78, 1, 65458, 79, 1, 0, 566 /* 535 */ 65439, 77, 1, 65460, 79, 1, 0, 567 /* 542 */ 65507, 79, 1, 65457, 80, 1, 0, 568 /* 549 */ 65439, 78, 1, 65459, 80, 1, 0, 569 /* 556 */ 65045, 1, 0, 570 /* 559 */ 65260, 1, 0, 571 /* 562 */ 65299, 1, 0, 572 /* 565 */ 65300, 1, 0, 573 /* 568 */ 65301, 1, 0, 574 /* 571 */ 65302, 1, 0, 575 /* 574 */ 65303, 1, 0, 576 /* 577 */ 65304, 1, 0, 577 /* 580 */ 65305, 1, 0, 578 /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0, 579 /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0, 580 /* 600 */ 65488, 13, 121, 65416, 1, 0, 581 /* 606 */ 65489, 13, 121, 65416, 1, 0, 582 /* 612 */ 65490, 13, 121, 65416, 1, 0, 583 /* 618 */ 65491, 13, 121, 65416, 1, 0, 584 /* 624 */ 65492, 13, 121, 65416, 1, 0, 585 /* 630 */ 65493, 13, 121, 65416, 1, 0, 586 /* 636 */ 65494, 13, 121, 65416, 1, 0, 587 /* 642 */ 65495, 13, 121, 65416, 1, 0, 588 /* 648 */ 65496, 13, 121, 65416, 1, 0, 589 /* 654 */ 65497, 13, 121, 65416, 1, 0, 590 /* 660 */ 65498, 13, 121, 65416, 1, 0, 591 /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0, 592 /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0, 593 /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0, 594 /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0, 595 /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0, 596 /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0, 597 /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0, 598 /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0, 599 /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0, 600 /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0, 601 /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0, 602 /* 765 */ 65488, 133, 65416, 1, 0, 603 /* 770 */ 65499, 134, 65416, 1, 0, 604 /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0, 605 /* 783 */ 65432, 1, 0, 606 /* 786 */ 65433, 1, 0, 607 /* 789 */ 65434, 1, 0, 608 /* 792 */ 65435, 1, 0, 609 /* 795 */ 65436, 1, 0, 610 /* 798 */ 65437, 1, 0, 611 /* 801 */ 65464, 1, 0, 612 /* 804 */ 65508, 1, 0, 613 /* 807 */ 65509, 1, 0, 614 /* 810 */ 65510, 1, 0, 615 /* 813 */ 65511, 1, 0, 616 /* 816 */ 65512, 1, 0, 617 /* 819 */ 65513, 1, 0, 618 /* 822 */ 65514, 1, 0, 619 /* 825 */ 65515, 1, 0, 620 /* 828 */ 65520, 1, 0, 621 /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0, 622 /* 839 */ 65136, 1, 3, 1, 2, 0, 623 /* 845 */ 65326, 1, 2, 0, 624 /* 849 */ 65080, 1, 3, 1, 2, 2, 0, 625 /* 856 */ 65136, 1, 2, 2, 0, 626 /* 861 */ 65080, 1, 2, 2, 2, 0, 627 /* 867 */ 65330, 2, 2, 2, 0, 628 /* 872 */ 65080, 1, 3, 2, 2, 0, 629 /* 878 */ 65358, 2, 2, 0, 630 /* 882 */ 65080, 1, 3, 1, 3, 2, 0, 631 /* 889 */ 65136, 1, 3, 2, 0, 632 /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0, 633 /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0, 634 /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0, 635 /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0, 636 /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0, 637 /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0, 638 /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0, 639 /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0, 640 /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0, 641 /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0, 642 /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0, 643 /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0, 644 /* 1038 */ 65344, 2, 2, 93, 2, 0, 645 /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0, 646 /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0, 647 /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0, 648 /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0, 649 /* 1080 */ 65439, 2, 0, 650 /* 1083 */ 65453, 2, 0, 651 /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0, 652 /* 1094 */ 65136, 1, 3, 1, 3, 0, 653 /* 1100 */ 65326, 1, 3, 0, 654 /* 1104 */ 5, 0, 655 /* 1106 */ 140, 65486, 13, 0, 656 /* 1110 */ 14, 0, 657 /* 1112 */ 126, 65501, 15, 0, 658 /* 1116 */ 10, 66, 0, 659 /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0, 660 /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0, 661 /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0, 662 /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0, 663 /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0, 664 /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0, 665 /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0, 666 /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0, 667 /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0, 668 /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0, 669 /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0, 670 /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0, 671 /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0, 672 /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0, 673 /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0, 674 /* 1359 */ 91, 0, 675 /* 1361 */ 98, 0, 676 /* 1363 */ 99, 0, 677 /* 1365 */ 100, 0, 678 /* 1367 */ 101, 0, 679 /* 1369 */ 102, 0, 680 /* 1371 */ 103, 0, 681 /* 1373 */ 104, 0, 682 /* 1375 */ 65374, 1, 1, 20, 75, 135, 0, 683 /* 1382 */ 65374, 1, 1, 21, 74, 136, 0, 684 /* 1389 */ 65374, 1, 1, 22, 73, 137, 0, 685 /* 1396 */ 65374, 1, 1, 23, 72, 138, 0, 686 /* 1403 */ 65374, 1, 1, 24, 71, 139, 0, 687 /* 1410 */ 65374, 1, 1, 25, 70, 140, 0, 688 /* 1417 */ 65374, 1, 1, 26, 69, 141, 0, 689 /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0, 690 /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0, 691 /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0, 692 /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0, 693 /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0, 694 /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0, 695 /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0, 696 /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0, 697 /* 1526 */ 157, 0, 698 /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0, 699 /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0, 700 /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0, 701 /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0, 702 /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0, 703 /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0, 704 /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0, 705 /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0, 706 /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0, 707 /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0, 708 /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0, 709 /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0, 710 /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0, 711 /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0, 712 /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0, 713 /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0, 714 /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0, 715 /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0, 716 /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0, 717 /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0, 718 /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0, 719 /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0, 720 /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0, 721 /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0, 722 /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0, 723 /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0, 724 /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0, 725 /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0, 726 /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0, 727 /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0, 728 /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0, 729 /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0, 730 /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0, 731 /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0, 732 /* 2455 */ 65487, 13, 121, 65416, 0, 733 /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0, 734 /* 2468 */ 65466, 1, 65486, 133, 65416, 0, 735 /* 2474 */ 65487, 133, 65416, 0, 736 /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, 737 /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, 738 /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0, 739 /* 2509 */ 65452, 1, 65500, 134, 65417, 0, 740 /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0, 741 /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0, 742 /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0, 743 /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0, 744 /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0, 745 /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0, 746 /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0, 747 /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0, 748 /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0, 749 /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0, 750 /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0, 751 /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0, 752 /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0, 753 /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0, 754 /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0, 755 /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0, 756 /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0, 757 /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0, 758 /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0, 759 /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0, 760 /* 2832 */ 26, 65446, 92, 65445, 0, 761 /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0, 762 /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0, 763 /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0, 764 /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0, 765 /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, 766 /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, 767 /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0, 768 /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0, 769 /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, 770 /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, 771 /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0, 772 /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0, 773 /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, 774 /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, 775 /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0, 776 /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0, 777 /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, 778 /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, 779 /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, 780 /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, 781 /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0, 782 /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, 783 /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, 784 /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, 785 /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, 786 /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0, 787 /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, 788 /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, 789 /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, 790 /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, 791 /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, 792 /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0, 793 /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, 794 /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, 795 /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, 796 /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, 797 /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, 798 /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0, 799 /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, 800 /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, 801 /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, 802 /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, 803 /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, 804 /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0, 805 /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, 806 /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, 807 /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, 808 /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, 809 /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, 810 /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0, 811 /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, 812 /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, 813 /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, 814 /* 3839 */ 65298, 80, 1, 65456, 0, 815 /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, 816 /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, 817 /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0, 818 /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, 819 /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, 820 /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0, 821 /* 3948 */ 65439, 80, 1, 65457, 0, 822 /* 3953 */ 28, 65457, 0, 823 /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, 824 /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, 825 /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, 826 /* 4002 */ 26, 65458, 80, 65457, 0, 827 /* 4007 */ 65439, 79, 1, 65458, 0, 828 /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0, 829 /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0, 830 /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0, 831 /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0, 832 /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0, 833 /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0, 834 /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0, 835 /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0, 836 /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0, 837 /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0, 838 /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0, 839 /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0, 840 /* 4114 */ 65445, 65470, 0, 841 /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0, 842 /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0, 843 /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0, 844 /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0, 845 /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0, 846 /* 4182 */ 65534, 0, 847 /* 4184 */ 65535, 0, 848}; 849 850static uint16_t ARMSubRegIdxLists[] = { 851 /* 0 */ 1, 2, 0, 852 /* 3 */ 1, 17, 18, 2, 0, 853 /* 8 */ 1, 3, 0, 854 /* 11 */ 1, 17, 18, 3, 0, 855 /* 16 */ 9, 10, 0, 856 /* 19 */ 17, 18, 0, 857 /* 22 */ 1, 17, 18, 2, 19, 20, 0, 858 /* 29 */ 1, 17, 18, 3, 21, 22, 0, 859 /* 36 */ 1, 2, 3, 13, 33, 37, 0, 860 /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0, 861 /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0, 862 /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0, 863 /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0, 864 /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0, 865 /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, 866 /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, 867 /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0, 868 /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0, 869 /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0, 870 /* 188 */ 1, 3, 5, 33, 43, 0, 871 /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0, 872 /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0, 873 /* 212 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 33, 43, 0, 874 /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0, 875 /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0, 876 /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0, 877 /* 260 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 33, 38, 43, 45, 51, 0, 878 /* 276 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 27, 28, 33, 38, 43, 45, 51, 0, 879 /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 880 /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 881 /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 882 /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 883 /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 27, 28, 8, 25, 26, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, 884}; 885 886static MCRegisterDesc ARMRegDesc[] = { // Descriptors 887 { 12, 0, 0, 0, 0 }, 888 { 1235, 16, 16, 2, 66945 }, 889 { 1268, 16, 16, 2, 66945 }, 890 { 1240, 16, 16, 2, 66945 }, 891 { 1199, 16, 16, 2, 66945 }, 892 { 1250, 16, 16, 2, 66945 }, 893 { 1226, 16, 16, 2, 17664 }, 894 { 1257, 16, 16, 2, 17664 }, 895 { 1205, 16, 16, 2, 66913 }, 896 { 1211, 16, 16, 2, 66913 }, 897 { 1232, 16, 16, 2, 66913 }, 898 { 1196, 16, 16, 2, 66913 }, 899 { 1223, 16, 1526, 2, 66913 }, 900 { 1245, 16, 16, 2, 66913 }, 901 { 119, 350, 4013, 19, 13250 }, 902 { 248, 357, 2479, 19, 13250 }, 903 { 363, 364, 3957, 19, 13250 }, 904 { 479, 378, 3845, 19, 13250 }, 905 { 605, 392, 3893, 19, 13250 }, 906 { 723, 406, 3724, 19, 13250 }, 907 { 837, 420, 3780, 19, 13250 }, 908 { 943, 434, 3604, 19, 13250 }, 909 { 1057, 448, 3664, 19, 13250 }, 910 { 1163, 462, 3484, 19, 13250 }, 911 { 9, 476, 3544, 19, 13250 }, 912 { 141, 490, 3364, 19, 13250 }, 913 { 282, 504, 3424, 19, 13250 }, 914 { 408, 518, 3244, 19, 13250 }, 915 { 523, 532, 3304, 19, 13250 }, 916 { 649, 546, 3149, 19, 13250 }, 917 { 768, 16, 3208, 2, 17761 }, 918 { 882, 16, 3078, 2, 17761 }, 919 { 988, 16, 3113, 2, 17761 }, 920 { 1102, 16, 3008, 2, 17761 }, 921 { 59, 16, 3043, 2, 17761 }, 922 { 192, 16, 2938, 2, 17761 }, 923 { 336, 16, 2973, 2, 17761 }, 924 { 456, 16, 2868, 2, 17761 }, 925 { 575, 16, 2903, 2, 17761 }, 926 { 697, 16, 2797, 2, 17761 }, 927 { 804, 16, 2837, 2, 17761 }, 928 { 914, 16, 2363, 2, 17761 }, 929 { 1024, 16, 2411, 2, 17761 }, 930 { 1134, 16, 2384, 2, 17761 }, 931 { 95, 16, 2429, 2, 17761 }, 932 { 224, 16, 2789, 2, 17761 }, 933 { 390, 16, 16, 2, 17761 }, 934 { 125, 16, 16, 2, 17761 }, 935 { 257, 16, 16, 2, 17761 }, 936 { 381, 16, 16, 2, 17761 }, 937 { 122, 353, 1112, 22, 2196 }, 938 { 254, 374, 775, 22, 2196 }, 939 { 378, 402, 314, 22, 2196 }, 940 { 500, 430, 244, 22, 2196 }, 941 { 629, 458, 234, 22, 2196 }, 942 { 744, 486, 224, 22, 2196 }, 943 { 861, 514, 214, 22, 2196 }, 944 { 964, 542, 204, 22, 2196 }, 945 { 1081, 804, 194, 0, 12818 }, 946 { 1184, 807, 184, 0, 12818 }, 947 { 35, 810, 174, 0, 12818 }, 948 { 168, 813, 164, 0, 12818 }, 949 { 312, 816, 154, 0, 12818 }, 950 { 436, 819, 591, 0, 12818 }, 951 { 555, 822, 2447, 0, 12818 }, 952 { 677, 825, 1106, 0, 12818 }, 953 { 128, 16, 1373, 2, 66913 }, 954 { 260, 16, 1371, 2, 66913 }, 955 { 384, 16, 1371, 2, 66913 }, 956 { 506, 16, 1369, 2, 66913 }, 957 { 632, 16, 1369, 2, 66913 }, 958 { 750, 16, 1367, 2, 66913 }, 959 { 864, 16, 1367, 2, 66913 }, 960 { 970, 16, 1365, 2, 66913 }, 961 { 1084, 16, 1365, 2, 66913 }, 962 { 1190, 16, 1363, 2, 66913 }, 963 { 39, 16, 1363, 2, 66913 }, 964 { 176, 16, 1361, 2, 66913 }, 965 { 316, 16, 1359, 2, 66913 }, 966 { 131, 16, 4021, 2, 65585 }, 967 { 269, 16, 4012, 2, 65585 }, 968 { 387, 16, 2490, 2, 65585 }, 969 { 509, 16, 2478, 2, 65585 }, 970 { 635, 16, 3974, 2, 65585 }, 971 { 753, 16, 3956, 2, 65585 }, 972 { 867, 16, 3863, 2, 65585 }, 973 { 973, 16, 3844, 2, 65585 }, 974 { 1087, 16, 3914, 2, 65585 }, 975 { 1193, 16, 3892, 2, 65585 }, 976 { 43, 16, 3745, 2, 65585 }, 977 { 180, 16, 3723, 2, 65585 }, 978 { 320, 16, 3803, 2, 65585 }, 979 { 440, 16, 3779, 2, 65585 }, 980 { 559, 16, 3627, 2, 65585 }, 981 { 681, 16, 3603, 2, 65585 }, 982 { 788, 16, 3687, 2, 65585 }, 983 { 898, 16, 3663, 2, 65585 }, 984 { 1008, 16, 3507, 2, 65585 }, 985 { 1118, 16, 3483, 2, 65585 }, 986 { 79, 16, 3567, 2, 65585 }, 987 { 212, 16, 3543, 2, 65585 }, 988 { 356, 16, 3387, 2, 65585 }, 989 { 472, 16, 3363, 2, 65585 }, 990 { 595, 16, 3447, 2, 65585 }, 991 { 713, 16, 3423, 2, 65585 }, 992 { 824, 16, 3267, 2, 65585 }, 993 { 930, 16, 3243, 2, 65585 }, 994 { 1044, 16, 3327, 2, 65585 }, 995 { 1150, 16, 3303, 2, 65585 }, 996 { 115, 16, 3172, 2, 65585 }, 997 { 244, 16, 3148, 2, 65585 }, 998 { 360, 367, 4015, 29, 5426 }, 999 { 476, 381, 2502, 29, 5426 }, 1000 { 602, 395, 3992, 29, 5426 }, 1001 { 720, 409, 3882, 29, 5426 }, 1002 { 834, 423, 3936, 29, 5426 }, 1003 { 940, 437, 3767, 29, 5426 }, 1004 { 1054, 451, 3827, 29, 5426 }, 1005 { 1160, 465, 3651, 29, 5426 }, 1006 { 6, 479, 3711, 29, 5426 }, 1007 { 151, 493, 3531, 29, 5426 }, 1008 { 278, 507, 3591, 29, 5426 }, 1009 { 404, 521, 3411, 29, 5426 }, 1010 { 519, 535, 3471, 29, 5426 }, 1011 { 645, 549, 3291, 29, 5426 }, 1012 { 764, 4007, 3351, 11, 17602 }, 1013 { 878, 3948, 3196, 11, 13522 }, 1014 { 984, 1080, 3231, 8, 17329 }, 1015 { 1098, 1080, 3101, 8, 17329 }, 1016 { 55, 1080, 3136, 8, 17329 }, 1017 { 204, 1080, 3031, 8, 17329 }, 1018 { 332, 1080, 3066, 8, 17329 }, 1019 { 452, 1080, 2961, 8, 17329 }, 1020 { 571, 1080, 2996, 8, 17329 }, 1021 { 693, 1080, 2891, 8, 17329 }, 1022 { 800, 1080, 2926, 8, 17329 }, 1023 { 910, 1080, 2820, 8, 17329 }, 1024 { 1020, 1080, 2858, 8, 17329 }, 1025 { 1130, 1080, 2401, 8, 17329 }, 1026 { 91, 1080, 2440, 8, 17329 }, 1027 { 236, 1080, 2791, 8, 17329 }, 1028 { 251, 1339, 1114, 168, 1044 }, 1029 { 375, 1319, 347, 168, 1044 }, 1030 { 497, 1299, 142, 168, 1044 }, 1031 { 626, 1279, 142, 168, 1044 }, 1032 { 741, 1259, 142, 168, 1044 }, 1033 { 858, 1239, 142, 168, 1044 }, 1034 { 961, 1219, 142, 168, 1044 }, 1035 { 1078, 1203, 142, 88, 1456 }, 1036 { 1181, 1191, 142, 76, 2114 }, 1037 { 32, 1179, 142, 76, 2114 }, 1038 { 164, 1167, 142, 76, 2114 }, 1039 { 308, 1155, 142, 76, 2114 }, 1040 { 432, 1143, 142, 76, 2114 }, 1041 { 551, 1131, 344, 76, 2114 }, 1042 { 673, 1119, 1108, 76, 2114 }, 1043 { 491, 2156, 16, 474, 4 }, 1044 { 620, 2101, 16, 474, 4 }, 1045 { 735, 2046, 16, 474, 4 }, 1046 { 852, 1991, 16, 474, 4 }, 1047 { 955, 1936, 16, 474, 4 }, 1048 { 1072, 1885, 16, 423, 272 }, 1049 { 1175, 1838, 16, 376, 512 }, 1050 { 26, 1795, 16, 333, 720 }, 1051 { 158, 1756, 16, 294, 1186 }, 1052 { 301, 1717, 16, 294, 1186 }, 1053 { 424, 1678, 16, 294, 1186 }, 1054 { 543, 1639, 16, 294, 1186 }, 1055 { 665, 1600, 16, 294, 1186 }, 1056 { 1219, 4114, 16, 16, 17856 }, 1057 { 263, 783, 16, 16, 8946 }, 1058 { 503, 786, 16, 16, 8946 }, 1059 { 747, 789, 16, 16, 8946 }, 1060 { 967, 792, 16, 16, 8946 }, 1061 { 1187, 795, 16, 16, 8946 }, 1062 { 172, 798, 16, 16, 8946 }, 1063 { 366, 1513, 1113, 63, 1570 }, 1064 { 482, 4169, 2511, 63, 1570 }, 1065 { 611, 1500, 778, 63, 1570 }, 1066 { 726, 4156, 770, 63, 1570 }, 1067 { 843, 1487, 317, 63, 1570 }, 1068 { 946, 4143, 660, 63, 1570 }, 1069 { 1063, 1474, 308, 63, 1570 }, 1070 { 1166, 4130, 654, 63, 1570 }, 1071 { 16, 1461, 302, 63, 1570 }, 1072 { 134, 4117, 648, 63, 1570 }, 1073 { 289, 1448, 296, 63, 1570 }, 1074 { 412, 4101, 642, 63, 1570 }, 1075 { 531, 1435, 290, 63, 1570 }, 1076 { 653, 4088, 636, 63, 1570 }, 1077 { 776, 1424, 284, 52, 1680 }, 1078 { 886, 4079, 630, 43, 1872 }, 1079 { 996, 1417, 278, 36, 2401 }, 1080 { 1106, 4072, 624, 36, 2401 }, 1081 { 67, 1410, 272, 36, 2401 }, 1082 { 184, 4065, 618, 36, 2401 }, 1083 { 344, 1403, 266, 36, 2401 }, 1084 { 460, 4058, 612, 36, 2401 }, 1085 { 583, 1396, 260, 36, 2401 }, 1086 { 701, 4051, 606, 36, 2401 }, 1087 { 812, 1389, 254, 36, 2401 }, 1088 { 918, 4044, 600, 36, 2401 }, 1089 { 1032, 1382, 765, 36, 2401 }, 1090 { 1138, 4037, 2455, 36, 2401 }, 1091 { 103, 1375, 2474, 36, 2401 }, 1092 { 216, 4030, 1107, 36, 2401 }, 1093 { 599, 1026, 4018, 212, 5314 }, 1094 { 717, 1014, 3953, 212, 5314 }, 1095 { 831, 1002, 4002, 212, 5314 }, 1096 { 937, 990, 3909, 212, 5314 }, 1097 { 1051, 978, 3909, 212, 5314 }, 1098 { 1157, 966, 3798, 212, 5314 }, 1099 { 3, 954, 3798, 212, 5314 }, 1100 { 148, 942, 3682, 212, 5314 }, 1101 { 275, 930, 3682, 212, 5314 }, 1102 { 401, 918, 3562, 212, 5314 }, 1103 { 515, 906, 3562, 212, 5314 }, 1104 { 641, 894, 3442, 212, 5314 }, 1105 { 760, 1070, 3442, 202, 17506 }, 1106 { 874, 1060, 3322, 202, 13426 }, 1107 { 980, 1052, 3322, 194, 14226 }, 1108 { 1094, 1044, 3226, 194, 13698 }, 1109 { 51, 1038, 3226, 188, 14049 }, 1110 { 200, 1038, 3131, 188, 14049 }, 1111 { 328, 1038, 3131, 188, 14049 }, 1112 { 448, 1038, 3061, 188, 14049 }, 1113 { 567, 1038, 3061, 188, 14049 }, 1114 { 689, 1038, 2991, 188, 14049 }, 1115 { 796, 1038, 2991, 188, 14049 }, 1116 { 906, 1038, 2921, 188, 14049 }, 1117 { 1016, 1038, 2921, 188, 14049 }, 1118 { 1126, 1038, 2832, 188, 14049 }, 1119 { 87, 1038, 2855, 188, 14049 }, 1120 { 232, 1038, 2794, 188, 14049 }, 1121 { 828, 2677, 4010, 276, 5170 }, 1122 { 934, 2659, 3951, 276, 5170 }, 1123 { 1048, 2641, 3951, 276, 5170 }, 1124 { 1154, 2623, 3842, 276, 5170 }, 1125 { 0, 2605, 3842, 276, 5170 }, 1126 { 145, 2587, 3743, 276, 5170 }, 1127 { 272, 2569, 3743, 276, 5170 }, 1128 { 398, 2551, 3625, 276, 5170 }, 1129 { 512, 2533, 3625, 276, 5170 }, 1130 { 638, 2515, 3505, 276, 5170 }, 1131 { 756, 2773, 3505, 260, 17378 }, 1132 { 870, 2757, 3385, 260, 13298 }, 1133 { 976, 2743, 3385, 246, 14114 }, 1134 { 1090, 2729, 3265, 246, 13586 }, 1135 { 47, 2717, 3265, 234, 13954 }, 1136 { 196, 2705, 3170, 234, 13778 }, 1137 { 324, 2695, 3170, 224, 13873 }, 1138 { 444, 2695, 3099, 224, 13873 }, 1139 { 563, 2695, 3099, 224, 13873 }, 1140 { 685, 2695, 3029, 224, 13873 }, 1141 { 792, 2695, 3029, 224, 13873 }, 1142 { 902, 2695, 2959, 224, 13873 }, 1143 { 1012, 2695, 2959, 224, 13873 }, 1144 { 1122, 2695, 2856, 224, 13873 }, 1145 { 83, 2695, 2856, 224, 13873 }, 1146 { 228, 2695, 2795, 224, 13873 }, 1147 { 369, 360, 2509, 22, 1956 }, 1148 { 614, 388, 583, 22, 1956 }, 1149 { 846, 416, 756, 22, 1956 }, 1150 { 1066, 444, 747, 22, 1956 }, 1151 { 19, 472, 738, 22, 1956 }, 1152 { 293, 500, 729, 22, 1956 }, 1153 { 535, 528, 720, 22, 1956 }, 1154 { 780, 3839, 711, 3, 2336 }, 1155 { 1000, 562, 702, 0, 8898 }, 1156 { 71, 565, 693, 0, 8898 }, 1157 { 348, 568, 684, 0, 8898 }, 1158 { 587, 571, 675, 0, 8898 }, 1159 { 816, 574, 666, 0, 8898 }, 1160 { 1036, 577, 2460, 0, 8898 }, 1161 { 107, 580, 2468, 0, 8898 }, 1162 { 608, 2343, 2488, 148, 900 }, 1163 { 840, 2323, 588, 148, 900 }, 1164 { 1060, 2303, 588, 148, 900 }, 1165 { 13, 2283, 588, 148, 900 }, 1166 { 286, 2263, 588, 148, 900 }, 1167 { 527, 2243, 588, 148, 900 }, 1168 { 772, 2225, 588, 130, 1328 }, 1169 { 992, 2211, 588, 116, 1776 }, 1170 { 63, 1588, 588, 104, 2034 }, 1171 { 340, 1576, 588, 104, 2034 }, 1172 { 579, 1564, 588, 104, 2034 }, 1173 { 808, 1552, 588, 104, 2034 }, 1174 { 1028, 1540, 588, 104, 2034 }, 1175 { 99, 1528, 2382, 104, 2034 }, 1176}; 1177 1178 // SPR Register Class... 1179 static uint16_t SPR[] = { 1180 ARM_S0, ARM_S2, ARM_S4, ARM_S6, ARM_S8, ARM_S10, ARM_S12, ARM_S14, ARM_S16, ARM_S18, ARM_S20, ARM_S22, ARM_S24, ARM_S26, ARM_S28, ARM_S30, ARM_S1, ARM_S3, ARM_S5, ARM_S7, ARM_S9, ARM_S11, ARM_S13, ARM_S15, ARM_S17, ARM_S19, ARM_S21, ARM_S23, ARM_S25, ARM_S27, ARM_S29, ARM_S31, 1181 }; 1182 1183 // SPR Bit set. 1184 static uint8_t SPRBits[] = { 1185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 1186 }; 1187 1188 // GPR Register Class... 1189 static uint16_t GPR[] = { 1190 ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, 1191 }; 1192 1193 // GPR Bit set. 1194 static uint8_t GPRBits[] = { 1195 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 1196 }; 1197 1198 // GPRwithAPSR Register Class... 1199 static uint16_t GPRwithAPSR[] = { 1200 ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, 1201 }; 1202 1203 // GPRwithAPSR Bit set. 1204 static uint8_t GPRwithAPSRBits[] = { 1205 0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 1206 }; 1207 1208 // SPR_8 Register Class... 1209 static uint16_t SPR_8[] = { 1210 ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, 1211 }; 1212 1213 // SPR_8 Bit set. 1214 static uint8_t SPR_8Bits[] = { 1215 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 1216 }; 1217 1218 // GPRnopc Register Class... 1219 static uint16_t GPRnopc[] = { 1220 ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, 1221 }; 1222 1223 // GPRnopc Bit set. 1224 static uint8_t GPRnopcBits[] = { 1225 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 1226 }; 1227 1228 // rGPR Register Class... 1229 static uint16_t rGPR[] = { 1230 ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, 1231 }; 1232 1233 // rGPR Bit set. 1234 static uint8_t rGPRBits[] = { 1235 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 1236 }; 1237 1238 // hGPR Register Class... 1239 static uint16_t hGPR[] = { 1240 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, 1241 }; 1242 1243 // hGPR Bit set. 1244 static uint8_t hGPRBits[] = { 1245 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 1246 }; 1247 1248 // tGPR Register Class... 1249 static uint16_t tGPR[] = { 1250 ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, 1251 }; 1252 1253 // tGPR Bit set. 1254 static uint8_t tGPRBits[] = { 1255 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 1256 }; 1257 1258 // GPRnopc_and_hGPR Register Class... 1259 static uint16_t GPRnopc_and_hGPR[] = { 1260 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, 1261 }; 1262 1263 // GPRnopc_and_hGPR Bit set. 1264 static uint8_t GPRnopc_and_hGPRBits[] = { 1265 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 1266 }; 1267 1268 // hGPR_and_rGPR Register Class... 1269 static uint16_t hGPR_and_rGPR[] = { 1270 ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, 1271 }; 1272 1273 // hGPR_and_rGPR Bit set. 1274 static uint8_t hGPR_and_rGPRBits[] = { 1275 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 1276 }; 1277 1278 // tcGPR Register Class... 1279 static uint16_t tcGPR[] = { 1280 ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, 1281 }; 1282 1283 // tcGPR Bit set. 1284 static uint8_t tcGPRBits[] = { 1285 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, 1286 }; 1287 1288 // tGPR_and_tcGPR Register Class... 1289 static uint16_t tGPR_and_tcGPR[] = { 1290 ARM_R0, ARM_R1, ARM_R2, ARM_R3, 1291 }; 1292 1293 // tGPR_and_tcGPR Bit set. 1294 static uint8_t tGPR_and_tcGPRBits[] = { 1295 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 1296 }; 1297 1298 // CCR Register Class... 1299 static uint16_t CCR[] = { 1300 ARM_CPSR, 1301 }; 1302 1303 // CCR Bit set. 1304 static uint8_t CCRBits[] = { 1305 0x08, 1306 }; 1307 1308 // GPRsp Register Class... 1309 static uint16_t GPRsp[] = { 1310 ARM_SP, 1311 }; 1312 1313 // GPRsp Bit set. 1314 static uint8_t GPRspBits[] = { 1315 0x00, 0x10, 1316 }; 1317 1318 // hGPR_and_tcGPR Register Class... 1319 static uint16_t hGPR_and_tcGPR[] = { 1320 ARM_R12, 1321 }; 1322 1323 // hGPR_and_tcGPR Bit set. 1324 static uint8_t hGPR_and_tcGPRBits[] = { 1325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 1326 }; 1327 1328 // DPR Register Class... 1329 static uint16_t DPR[] = { 1330 ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, 1331 }; 1332 1333 // DPR Bit set. 1334 static uint8_t DPRBits[] = { 1335 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 1336 }; 1337 1338 // DPR_VFP2 Register Class... 1339 static uint16_t DPR_VFP2[] = { 1340 ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, 1341 }; 1342 1343 // DPR_VFP2 Bit set. 1344 static uint8_t DPR_VFP2Bits[] = { 1345 0x00, 0xc0, 0xff, 0x3f, 1346 }; 1347 1348 // DPR_8 Register Class... 1349 static uint16_t DPR_8[] = { 1350 ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, 1351 }; 1352 1353 // DPR_8 Bit set. 1354 static uint8_t DPR_8Bits[] = { 1355 0x00, 0xc0, 0x3f, 1356 }; 1357 1358 // GPRPair Register Class... 1359 static uint16_t GPRPair[] = { 1360 ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, 1361 }; 1362 1363 // GPRPair Bit set. 1364 static uint8_t GPRPairBits[] = { 1365 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 1366 }; 1367 1368 // GPRPair_with_gsub_1_in_rGPR Register Class... 1369 static uint16_t GPRPair_with_gsub_1_in_rGPR[] = { 1370 ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, 1371 }; 1372 1373 // GPRPair_with_gsub_1_in_rGPR Bit set. 1374 static uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = { 1375 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 1376 }; 1377 1378 // GPRPair_with_gsub_0_in_tGPR Register Class... 1379 static uint16_t GPRPair_with_gsub_0_in_tGPR[] = { 1380 ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, 1381 }; 1382 1383 // GPRPair_with_gsub_0_in_tGPR Bit set. 1384 static uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { 1385 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 1386 }; 1387 1388 // GPRPair_with_gsub_0_in_hGPR Register Class... 1389 static uint16_t GPRPair_with_gsub_0_in_hGPR[] = { 1390 ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, 1391 }; 1392 1393 // GPRPair_with_gsub_0_in_hGPR Bit set. 1394 static uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { 1395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 1396 }; 1397 1398 // GPRPair_with_gsub_0_in_tcGPR Register Class... 1399 static uint16_t GPRPair_with_gsub_0_in_tcGPR[] = { 1400 ARM_R0_R1, ARM_R2_R3, ARM_R12_SP, 1401 }; 1402 1403 // GPRPair_with_gsub_0_in_tcGPR Bit set. 1404 static uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { 1405 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 1406 }; 1407 1408 // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class... 1409 static uint16_t GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = { 1410 ARM_R8_R9, ARM_R10_R11, 1411 }; 1412 1413 // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set. 1414 static uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = { 1415 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 1416 }; 1417 1418 // GPRPair_with_gsub_1_in_tcGPR Register Class... 1419 static uint16_t GPRPair_with_gsub_1_in_tcGPR[] = { 1420 ARM_R0_R1, ARM_R2_R3, 1421 }; 1422 1423 // GPRPair_with_gsub_1_in_tcGPR Bit set. 1424 static uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { 1425 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 1426 }; 1427 1428 // GPRPair_with_gsub_1_in_GPRsp Register Class... 1429 static uint16_t GPRPair_with_gsub_1_in_GPRsp[] = { 1430 ARM_R12_SP, 1431 }; 1432 1433 // GPRPair_with_gsub_1_in_GPRsp Bit set. 1434 static uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { 1435 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 1436 }; 1437 1438 // DPairSpc Register Class... 1439 static uint16_t DPairSpc[] = { 1440 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, 1441 }; 1442 1443 // DPairSpc Bit set. 1444 static uint8_t DPairSpcBits[] = { 1445 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 1446 }; 1447 1448 // DPairSpc_with_ssub_0 Register Class... 1449 static uint16_t DPairSpc_with_ssub_0[] = { 1450 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, 1451 }; 1452 1453 // DPairSpc_with_ssub_0 Bit set. 1454 static uint8_t DPairSpc_with_ssub_0Bits[] = { 1455 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 1456 }; 1457 1458 // DPairSpc_with_dsub_2_then_ssub_0 Register Class... 1459 static uint16_t DPairSpc_with_dsub_2_then_ssub_0[] = { 1460 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, 1461 }; 1462 1463 // DPairSpc_with_dsub_2_then_ssub_0 Bit set. 1464 static uint8_t DPairSpc_with_dsub_2_then_ssub_0Bits[] = { 1465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 1466 }; 1467 1468 // DPairSpc_with_dsub_0_in_DPR_8 Register Class... 1469 static uint16_t DPairSpc_with_dsub_0_in_DPR_8[] = { 1470 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, 1471 }; 1472 1473 // DPairSpc_with_dsub_0_in_DPR_8 Bit set. 1474 static uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { 1475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 1476 }; 1477 1478 // DPairSpc_with_dsub_2_in_DPR_8 Register Class... 1479 static uint16_t DPairSpc_with_dsub_2_in_DPR_8[] = { 1480 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, 1481 }; 1482 1483 // DPairSpc_with_dsub_2_in_DPR_8 Bit set. 1484 static uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { 1485 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 1486 }; 1487 1488 // DPair Register Class... 1489 static uint16_t DPair[] = { 1490 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15, 1491 }; 1492 1493 // DPair Bit set. 1494 static uint8_t DPairBits[] = { 1495 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 1496 }; 1497 1498 // DPair_with_ssub_0 Register Class... 1499 static uint16_t DPair_with_ssub_0[] = { 1500 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, 1501 }; 1502 1503 // DPair_with_ssub_0 Bit set. 1504 static uint8_t DPair_with_ssub_0Bits[] = { 1505 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 1506 }; 1507 1508 // QPR Register Class... 1509 static uint16_t QPR[] = { 1510 ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 1511 }; 1512 1513 // QPR Bit set. 1514 static uint8_t QPRBits[] = { 1515 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 1516 }; 1517 1518 // DPair_with_ssub_2 Register Class... 1519 static uint16_t DPair_with_ssub_2[] = { 1520 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, 1521 }; 1522 1523 // DPair_with_ssub_2 Bit set. 1524 static uint8_t DPair_with_ssub_2Bits[] = { 1525 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 1526 }; 1527 1528 // DPair_with_dsub_0_in_DPR_8 Register Class... 1529 static uint16_t DPair_with_dsub_0_in_DPR_8[] = { 1530 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, 1531 }; 1532 1533 // DPair_with_dsub_0_in_DPR_8 Bit set. 1534 static uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { 1535 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 1536 }; 1537 1538 // QPR_VFP2 Register Class... 1539 static uint16_t QPR_VFP2[] = { 1540 ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, 1541 }; 1542 1543 // QPR_VFP2 Bit set. 1544 static uint8_t QPR_VFP2Bits[] = { 1545 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 1546 }; 1547 1548 // DPair_with_dsub_1_in_DPR_8 Register Class... 1549 static uint16_t DPair_with_dsub_1_in_DPR_8[] = { 1550 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, 1551 }; 1552 1553 // DPair_with_dsub_1_in_DPR_8 Bit set. 1554 static uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { 1555 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 1556 }; 1557 1558 // QPR_8 Register Class... 1559 static uint16_t QPR_8[] = { 1560 ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, 1561 }; 1562 1563 // QPR_8 Bit set. 1564 static uint8_t QPR_8Bits[] = { 1565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 1566 }; 1567 1568 // DTriple Register Class... 1569 static uint16_t DTriple[] = { 1570 ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31, 1571 }; 1572 1573 // DTriple Bit set. 1574 static uint8_t DTripleBits[] = { 1575 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, 1576 }; 1577 1578 // DTripleSpc Register Class... 1579 static uint16_t DTripleSpc[] = { 1580 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, 1581 }; 1582 1583 // DTripleSpc Bit set. 1584 static uint8_t DTripleSpcBits[] = { 1585 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 1586 }; 1587 1588 // DTripleSpc_with_ssub_0 Register Class... 1589 static uint16_t DTripleSpc_with_ssub_0[] = { 1590 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, 1591 }; 1592 1593 // DTripleSpc_with_ssub_0 Bit set. 1594 static uint8_t DTripleSpc_with_ssub_0Bits[] = { 1595 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 1596 }; 1597 1598 // DTriple_with_ssub_0 Register Class... 1599 static uint16_t DTriple_with_ssub_0[] = { 1600 ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, 1601 }; 1602 1603 // DTriple_with_ssub_0 Bit set. 1604 static uint8_t DTriple_with_ssub_0Bits[] = { 1605 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 1606 }; 1607 1608 // DTriple_with_dsub_1_dsub_2_in_QPR Register Class... 1609 static uint16_t DTriple_with_dsub_1_dsub_2_in_QPR[] = { 1610 ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, 1611 }; 1612 1613 // DTriple_with_dsub_1_dsub_2_in_QPR Bit set. 1614 static uint8_t DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { 1615 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, 1616 }; 1617 1618 // DTriple_with_qsub_0_in_QPR Register Class... 1619 static uint16_t DTriple_with_qsub_0_in_QPR[] = { 1620 ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, 1621 }; 1622 1623 // DTriple_with_qsub_0_in_QPR Bit set. 1624 static uint8_t DTriple_with_qsub_0_in_QPRBits[] = { 1625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 1626 }; 1627 1628 // DTriple_with_ssub_2 Register Class... 1629 static uint16_t DTriple_with_ssub_2[] = { 1630 ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, 1631 }; 1632 1633 // DTriple_with_ssub_2 Bit set. 1634 static uint8_t DTriple_with_ssub_2Bits[] = { 1635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 1636 }; 1637 1638 // DTripleSpc_with_dsub_2_then_ssub_0 Register Class... 1639 static uint16_t DTripleSpc_with_dsub_2_then_ssub_0[] = { 1640 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, 1641 }; 1642 1643 // DTripleSpc_with_dsub_2_then_ssub_0 Bit set. 1644 static uint8_t DTripleSpc_with_dsub_2_then_ssub_0Bits[] = { 1645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 1646 }; 1647 1648 // DTriple_with_dsub_2_then_ssub_0 Register Class... 1649 static uint16_t DTriple_with_dsub_2_then_ssub_0[] = { 1650 ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, 1651 }; 1652 1653 // DTriple_with_dsub_2_then_ssub_0 Bit set. 1654 static uint8_t DTriple_with_dsub_2_then_ssub_0Bits[] = { 1655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 1656 }; 1657 1658 // DTripleSpc_with_dsub_4_then_ssub_0 Register Class... 1659 static uint16_t DTripleSpc_with_dsub_4_then_ssub_0[] = { 1660 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, 1661 }; 1662 1663 // DTripleSpc_with_dsub_4_then_ssub_0 Bit set. 1664 static uint8_t DTripleSpc_with_dsub_4_then_ssub_0Bits[] = { 1665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 1666 }; 1667 1668 // DTripleSpc_with_dsub_0_in_DPR_8 Register Class... 1669 static uint16_t DTripleSpc_with_dsub_0_in_DPR_8[] = { 1670 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, 1671 }; 1672 1673 // DTripleSpc_with_dsub_0_in_DPR_8 Bit set. 1674 static uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { 1675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 1676 }; 1677 1678 // DTriple_with_dsub_0_in_DPR_8 Register Class... 1679 static uint16_t DTriple_with_dsub_0_in_DPR_8[] = { 1680 ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, 1681 }; 1682 1683 // DTriple_with_dsub_0_in_DPR_8 Bit set. 1684 static uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { 1685 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 1686 }; 1687 1688 // DTriple_with_qsub_0_in_QPR_VFP2 Register Class... 1689 static uint16_t DTriple_with_qsub_0_in_QPR_VFP2[] = { 1690 ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, 1691 }; 1692 1693 // DTriple_with_qsub_0_in_QPR_VFP2 Bit set. 1694 static uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = { 1695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 1696 }; 1697 1698 // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class... 1699 static uint16_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = { 1700 ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, 1701 }; 1702 1703 // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set. 1704 static uint8_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { 1705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 1706 }; 1707 1708 // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class... 1709 static uint16_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2[] = { 1710 ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, 1711 }; 1712 1713 // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set. 1714 static uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = { 1715 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 1716 }; 1717 1718 // DTriple_with_dsub_1_in_DPR_8 Register Class... 1719 static uint16_t DTriple_with_dsub_1_in_DPR_8[] = { 1720 ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, 1721 }; 1722 1723 // DTriple_with_dsub_1_in_DPR_8 Bit set. 1724 static uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { 1725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 1726 }; 1727 1728 // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Register Class... 1729 static uint16_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR[] = { 1730 ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, 1731 }; 1732 1733 // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Bit set. 1734 static uint8_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits[] = { 1735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 1736 }; 1737 1738 // DTripleSpc_with_dsub_2_in_DPR_8 Register Class... 1739 static uint16_t DTripleSpc_with_dsub_2_in_DPR_8[] = { 1740 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, 1741 }; 1742 1743 // DTripleSpc_with_dsub_2_in_DPR_8 Bit set. 1744 static uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { 1745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 1746 }; 1747 1748 // DTriple_with_dsub_2_in_DPR_8 Register Class... 1749 static uint16_t DTriple_with_dsub_2_in_DPR_8[] = { 1750 ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, 1751 }; 1752 1753 // DTriple_with_dsub_2_in_DPR_8 Bit set. 1754 static uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { 1755 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 1756 }; 1757 1758 // DTripleSpc_with_dsub_4_in_DPR_8 Register Class... 1759 static uint16_t DTripleSpc_with_dsub_4_in_DPR_8[] = { 1760 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, 1761 }; 1762 1763 // DTripleSpc_with_dsub_4_in_DPR_8 Bit set. 1764 static uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { 1765 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 1766 }; 1767 1768 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class... 1769 static uint16_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = { 1770 ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, 1771 }; 1772 1773 // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set. 1774 static uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { 1775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 1776 }; 1777 1778 // DTriple_with_qsub_0_in_QPR_8 Register Class... 1779 static uint16_t DTriple_with_qsub_0_in_QPR_8[] = { 1780 ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, 1781 }; 1782 1783 // DTriple_with_qsub_0_in_QPR_8 Bit set. 1784 static uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { 1785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 1786 }; 1787 1788 // DTriple_with_dsub_1_dsub_2_in_QPR_8 Register Class... 1789 static uint16_t DTriple_with_dsub_1_dsub_2_in_QPR_8[] = { 1790 ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, 1791 }; 1792 1793 // DTriple_with_dsub_1_dsub_2_in_QPR_8 Bit set. 1794 static uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_8Bits[] = { 1795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 1796 }; 1797 1798 // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class... 1799 static uint16_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = { 1800 ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, 1801 }; 1802 1803 // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set. 1804 static uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = { 1805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 1806 }; 1807 1808 // DQuadSpc Register Class... 1809 static uint16_t DQuadSpc[] = { 1810 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, 1811 }; 1812 1813 // DQuadSpc Bit set. 1814 static uint8_t DQuadSpcBits[] = { 1815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 1816 }; 1817 1818 // DQuadSpc_with_ssub_0 Register Class... 1819 static uint16_t DQuadSpc_with_ssub_0[] = { 1820 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, 1821 }; 1822 1823 // DQuadSpc_with_ssub_0 Bit set. 1824 static uint8_t DQuadSpc_with_ssub_0Bits[] = { 1825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 1826 }; 1827 1828 // DQuadSpc_with_dsub_2_then_ssub_0 Register Class... 1829 static uint16_t DQuadSpc_with_dsub_2_then_ssub_0[] = { 1830 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, 1831 }; 1832 1833 // DQuadSpc_with_dsub_2_then_ssub_0 Bit set. 1834 static uint8_t DQuadSpc_with_dsub_2_then_ssub_0Bits[] = { 1835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 1836 }; 1837 1838 // DQuadSpc_with_dsub_4_then_ssub_0 Register Class... 1839 static uint16_t DQuadSpc_with_dsub_4_then_ssub_0[] = { 1840 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, 1841 }; 1842 1843 // DQuadSpc_with_dsub_4_then_ssub_0 Bit set. 1844 static uint8_t DQuadSpc_with_dsub_4_then_ssub_0Bits[] = { 1845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 1846 }; 1847 1848 // DQuadSpc_with_dsub_0_in_DPR_8 Register Class... 1849 static uint16_t DQuadSpc_with_dsub_0_in_DPR_8[] = { 1850 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, 1851 }; 1852 1853 // DQuadSpc_with_dsub_0_in_DPR_8 Bit set. 1854 static uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { 1855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 1856 }; 1857 1858 // DQuadSpc_with_dsub_2_in_DPR_8 Register Class... 1859 static uint16_t DQuadSpc_with_dsub_2_in_DPR_8[] = { 1860 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, 1861 }; 1862 1863 // DQuadSpc_with_dsub_2_in_DPR_8 Bit set. 1864 static uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { 1865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 1866 }; 1867 1868 // DQuadSpc_with_dsub_4_in_DPR_8 Register Class... 1869 static uint16_t DQuadSpc_with_dsub_4_in_DPR_8[] = { 1870 ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, 1871 }; 1872 1873 // DQuadSpc_with_dsub_4_in_DPR_8 Bit set. 1874 static uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { 1875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 1876 }; 1877 1878 // DQuad Register Class... 1879 static uint16_t DQuad[] = { 1880 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15, 1881 }; 1882 1883 // DQuad Bit set. 1884 static uint8_t DQuadBits[] = { 1885 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 1886 }; 1887 1888 // DQuad_with_ssub_0 Register Class... 1889 static uint16_t DQuad_with_ssub_0[] = { 1890 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, 1891 }; 1892 1893 // DQuad_with_ssub_0 Bit set. 1894 static uint8_t DQuad_with_ssub_0Bits[] = { 1895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 1896 }; 1897 1898 // DQuad_with_ssub_2 Register Class... 1899 static uint16_t DQuad_with_ssub_2[] = { 1900 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, 1901 }; 1902 1903 // DQuad_with_ssub_2 Bit set. 1904 static uint8_t DQuad_with_ssub_2Bits[] = { 1905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 1906 }; 1907 1908 // QQPR Register Class... 1909 static uint16_t QQPR[] = { 1910 ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, 1911 }; 1912 1913 // QQPR Bit set. 1914 static uint8_t QQPRBits[] = { 1915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 1916 }; 1917 1918 // DQuad_with_dsub_1_dsub_2_in_QPR Register Class... 1919 static uint16_t DQuad_with_dsub_1_dsub_2_in_QPR[] = { 1920 ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, 1921 }; 1922 1923 // DQuad_with_dsub_1_dsub_2_in_QPR Bit set. 1924 static uint8_t DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { 1925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 1926 }; 1927 1928 // DQuad_with_dsub_2_then_ssub_0 Register Class... 1929 static uint16_t DQuad_with_dsub_2_then_ssub_0[] = { 1930 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, 1931 }; 1932 1933 // DQuad_with_dsub_2_then_ssub_0 Bit set. 1934 static uint8_t DQuad_with_dsub_2_then_ssub_0Bits[] = { 1935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 1936 }; 1937 1938 // DQuad_with_dsub_3_then_ssub_0 Register Class... 1939 static uint16_t DQuad_with_dsub_3_then_ssub_0[] = { 1940 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, 1941 }; 1942 1943 // DQuad_with_dsub_3_then_ssub_0 Bit set. 1944 static uint8_t DQuad_with_dsub_3_then_ssub_0Bits[] = { 1945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 1946 }; 1947 1948 // DQuad_with_dsub_0_in_DPR_8 Register Class... 1949 static uint16_t DQuad_with_dsub_0_in_DPR_8[] = { 1950 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, 1951 }; 1952 1953 // DQuad_with_dsub_0_in_DPR_8 Bit set. 1954 static uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { 1955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 1956 }; 1957 1958 // DQuad_with_qsub_0_in_QPR_VFP2 Register Class... 1959 static uint16_t DQuad_with_qsub_0_in_QPR_VFP2[] = { 1960 ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, 1961 }; 1962 1963 // DQuad_with_qsub_0_in_QPR_VFP2 Bit set. 1964 static uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = { 1965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 1966 }; 1967 1968 // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... 1969 static uint16_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { 1970 ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, 1971 }; 1972 1973 // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. 1974 static uint8_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { 1975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 1976 }; 1977 1978 // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class... 1979 static uint16_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2[] = { 1980 ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, 1981 }; 1982 1983 // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set. 1984 static uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = { 1985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 1986 }; 1987 1988 // DQuad_with_dsub_1_in_DPR_8 Register Class... 1989 static uint16_t DQuad_with_dsub_1_in_DPR_8[] = { 1990 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, 1991 }; 1992 1993 // DQuad_with_dsub_1_in_DPR_8 Bit set. 1994 static uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { 1995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 1996 }; 1997 1998 // DQuad_with_qsub_1_in_QPR_VFP2 Register Class... 1999 static uint16_t DQuad_with_qsub_1_in_QPR_VFP2[] = { 2000 ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, 2001 }; 2002 2003 // DQuad_with_qsub_1_in_QPR_VFP2 Bit set. 2004 static uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = { 2005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 2006 }; 2007 2008 // DQuad_with_dsub_2_in_DPR_8 Register Class... 2009 static uint16_t DQuad_with_dsub_2_in_DPR_8[] = { 2010 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, 2011 }; 2012 2013 // DQuad_with_dsub_2_in_DPR_8 Bit set. 2014 static uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { 2015 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 2016 }; 2017 2018 // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... 2019 static uint16_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { 2020 ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, 2021 }; 2022 2023 // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. 2024 static uint8_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { 2025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 2026 }; 2027 2028 // DQuad_with_dsub_3_in_DPR_8 Register Class... 2029 static uint16_t DQuad_with_dsub_3_in_DPR_8[] = { 2030 ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, 2031 }; 2032 2033 // DQuad_with_dsub_3_in_DPR_8 Bit set. 2034 static uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { 2035 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 2036 }; 2037 2038 // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... 2039 static uint16_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { 2040 ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, 2041 }; 2042 2043 // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. 2044 static uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { 2045 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 2046 }; 2047 2048 // DQuad_with_qsub_0_in_QPR_8 Register Class... 2049 static uint16_t DQuad_with_qsub_0_in_QPR_8[] = { 2050 ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, 2051 }; 2052 2053 // DQuad_with_qsub_0_in_QPR_8 Bit set. 2054 static uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { 2055 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 2056 }; 2057 2058 // DQuad_with_dsub_1_dsub_2_in_QPR_8 Register Class... 2059 static uint16_t DQuad_with_dsub_1_dsub_2_in_QPR_8[] = { 2060 ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, 2061 }; 2062 2063 // DQuad_with_dsub_1_dsub_2_in_QPR_8 Bit set. 2064 static uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_8Bits[] = { 2065 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 2066 }; 2067 2068 // DQuad_with_qsub_1_in_QPR_8 Register Class... 2069 static uint16_t DQuad_with_qsub_1_in_QPR_8[] = { 2070 ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, 2071 }; 2072 2073 // DQuad_with_qsub_1_in_QPR_8 Bit set. 2074 static uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { 2075 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 2076 }; 2077 2078 // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... 2079 static uint16_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { 2080 ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, 2081 }; 2082 2083 // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. 2084 static uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { 2085 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 2086 }; 2087 2088 // QQQQPR Register Class... 2089 static uint16_t QQQQPR[] = { 2090 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15, 2091 }; 2092 2093 // QQQQPR Bit set. 2094 static uint8_t QQQQPRBits[] = { 2095 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 2096 }; 2097 2098 // QQQQPR_with_ssub_0 Register Class... 2099 static uint16_t QQQQPR_with_ssub_0[] = { 2100 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, 2101 }; 2102 2103 // QQQQPR_with_ssub_0 Bit set. 2104 static uint8_t QQQQPR_with_ssub_0Bits[] = { 2105 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 2106 }; 2107 2108 // QQQQPR_with_dsub_2_then_ssub_0 Register Class... 2109 static uint16_t QQQQPR_with_dsub_2_then_ssub_0[] = { 2110 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, 2111 }; 2112 2113 // QQQQPR_with_dsub_2_then_ssub_0 Bit set. 2114 static uint8_t QQQQPR_with_dsub_2_then_ssub_0Bits[] = { 2115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 2116 }; 2117 2118 // QQQQPR_with_dsub_5_then_ssub_0 Register Class... 2119 static uint16_t QQQQPR_with_dsub_5_then_ssub_0[] = { 2120 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, 2121 }; 2122 2123 // QQQQPR_with_dsub_5_then_ssub_0 Bit set. 2124 static uint8_t QQQQPR_with_dsub_5_then_ssub_0Bits[] = { 2125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 2126 }; 2127 2128 // QQQQPR_with_dsub_7_then_ssub_0 Register Class... 2129 static uint16_t QQQQPR_with_dsub_7_then_ssub_0[] = { 2130 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, 2131 }; 2132 2133 // QQQQPR_with_dsub_7_then_ssub_0 Bit set. 2134 static uint8_t QQQQPR_with_dsub_7_then_ssub_0Bits[] = { 2135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 2136 }; 2137 2138 // QQQQPR_with_dsub_0_in_DPR_8 Register Class... 2139 static uint16_t QQQQPR_with_dsub_0_in_DPR_8[] = { 2140 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, 2141 }; 2142 2143 // QQQQPR_with_dsub_0_in_DPR_8 Bit set. 2144 static uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = { 2145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 2146 }; 2147 2148 // QQQQPR_with_dsub_2_in_DPR_8 Register Class... 2149 static uint16_t QQQQPR_with_dsub_2_in_DPR_8[] = { 2150 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, 2151 }; 2152 2153 // QQQQPR_with_dsub_2_in_DPR_8 Bit set. 2154 static uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = { 2155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 2156 }; 2157 2158 // QQQQPR_with_dsub_4_in_DPR_8 Register Class... 2159 static uint16_t QQQQPR_with_dsub_4_in_DPR_8[] = { 2160 ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, 2161 }; 2162 2163 // QQQQPR_with_dsub_4_in_DPR_8 Bit set. 2164 static uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = { 2165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 2166 }; 2167 2168 // QQQQPR_with_dsub_6_in_DPR_8 Register Class... 2169 static uint16_t QQQQPR_with_dsub_6_in_DPR_8[] = { 2170 ARM_Q0_Q1_Q2_Q3, 2171 }; 2172 2173 // QQQQPR_with_dsub_6_in_DPR_8 Bit set. 2174 static uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = { 2175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 2176 }; 2177 2178static MCRegisterClass ARMMCRegisterClasses[] = { 2179 { "SPR", SPR, SPRBits, 32, sizeof(SPRBits), ARM_SPRRegClassID, 4, 4, 1, 1 }, 2180 { "GPR", GPR, GPRBits, 16, sizeof(GPRBits), ARM_GPRRegClassID, 4, 4, 1, 1 }, 2181 { "GPRwithAPSR", GPRwithAPSR, GPRwithAPSRBits, 16, sizeof(GPRwithAPSRBits), ARM_GPRwithAPSRRegClassID, 4, 4, 1, 1 }, 2182 { "SPR_8", SPR_8, SPR_8Bits, 16, sizeof(SPR_8Bits), ARM_SPR_8RegClassID, 4, 4, 1, 1 }, 2183 { "GPRnopc", GPRnopc, GPRnopcBits, 15, sizeof(GPRnopcBits), ARM_GPRnopcRegClassID, 4, 4, 1, 1 }, 2184 { "rGPR", rGPR, rGPRBits, 14, sizeof(rGPRBits), ARM_rGPRRegClassID, 4, 4, 1, 1 }, 2185 { "hGPR", hGPR, hGPRBits, 8, sizeof(hGPRBits), ARM_hGPRRegClassID, 4, 4, 1, 1 }, 2186 { "tGPR", tGPR, tGPRBits, 8, sizeof(tGPRBits), ARM_tGPRRegClassID, 4, 4, 1, 1 }, 2187 { "GPRnopc_and_hGPR", GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 7, sizeof(GPRnopc_and_hGPRBits), ARM_GPRnopc_and_hGPRRegClassID, 4, 4, 1, 1 }, 2188 { "hGPR_and_rGPR", hGPR_and_rGPR, hGPR_and_rGPRBits, 6, sizeof(hGPR_and_rGPRBits), ARM_hGPR_and_rGPRRegClassID, 4, 4, 1, 1 }, 2189 { "tcGPR", tcGPR, tcGPRBits, 5, sizeof(tcGPRBits), ARM_tcGPRRegClassID, 4, 4, 1, 1 }, 2190 { "tGPR_and_tcGPR", tGPR_and_tcGPR, tGPR_and_tcGPRBits, 4, sizeof(tGPR_and_tcGPRBits), ARM_tGPR_and_tcGPRRegClassID, 4, 4, 1, 1 }, 2191 { "CCR", CCR, CCRBits, 1, sizeof(CCRBits), ARM_CCRRegClassID, 4, 4, -1, 0 }, 2192 { "GPRsp", GPRsp, GPRspBits, 1, sizeof(GPRspBits), ARM_GPRspRegClassID, 4, 4, 1, 1 }, 2193 { "hGPR_and_tcGPR", hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1, sizeof(hGPR_and_tcGPRBits), ARM_hGPR_and_tcGPRRegClassID, 4, 4, 1, 1 }, 2194 { "DPR", DPR, DPRBits, 32, sizeof(DPRBits), ARM_DPRRegClassID, 8, 8, 1, 1 }, 2195 { "DPR_VFP2", DPR_VFP2, DPR_VFP2Bits, 16, sizeof(DPR_VFP2Bits), ARM_DPR_VFP2RegClassID, 8, 8, 1, 1 }, 2196 { "DPR_8", DPR_8, DPR_8Bits, 8, sizeof(DPR_8Bits), ARM_DPR_8RegClassID, 8, 8, 1, 1 }, 2197 { "GPRPair", GPRPair, GPRPairBits, 7, sizeof(GPRPairBits), ARM_GPRPairRegClassID, 8, 8, 1, 1 }, 2198 { "GPRPair_with_gsub_1_in_rGPR", GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM_GPRPair_with_gsub_1_in_rGPRRegClassID, 8, 8, 1, 1 }, 2199 { "GPRPair_with_gsub_0_in_tGPR", GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM_GPRPair_with_gsub_0_in_tGPRRegClassID, 8, 8, 1, 1 }, 2200 { "GPRPair_with_gsub_0_in_hGPR", GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM_GPRPair_with_gsub_0_in_hGPRRegClassID, 8, 8, 1, 1 }, 2201 { "GPRPair_with_gsub_0_in_tcGPR", GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID, 8, 8, 1, 1 }, 2202 { "GPRPair_with_gsub_1_in_hGPR_and_rGPR", GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 8, 8, 1, 1 }, 2203 { "GPRPair_with_gsub_1_in_tcGPR", GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID, 8, 8, 1, 1 }, 2204 { "GPRPair_with_gsub_1_in_GPRsp", GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM_GPRPair_with_gsub_1_in_GPRspRegClassID, 8, 8, 1, 1 }, 2205 { "DPairSpc", DPairSpc, DPairSpcBits, 30, sizeof(DPairSpcBits), ARM_DPairSpcRegClassID, 16, 8, 1, 1 }, 2206 { "DPairSpc_with_ssub_0", DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM_DPairSpc_with_ssub_0RegClassID, 16, 8, 1, 1 }, 2207 { "DPairSpc_with_dsub_2_then_ssub_0", DPairSpc_with_dsub_2_then_ssub_0, DPairSpc_with_dsub_2_then_ssub_0Bits, 14, sizeof(DPairSpc_with_dsub_2_then_ssub_0Bits), ARM_DPairSpc_with_dsub_2_then_ssub_0RegClassID, 16, 8, 1, 1 }, 2208 { "DPairSpc_with_dsub_0_in_DPR_8", DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID, 16, 8, 1, 1 }, 2209 { "DPairSpc_with_dsub_2_in_DPR_8", DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID, 16, 8, 1, 1 }, 2210 { "DPair", DPair, DPairBits, 31, sizeof(DPairBits), ARM_DPairRegClassID, 16, 16, 1, 1 }, 2211 { "DPair_with_ssub_0", DPair_with_ssub_0, DPair_with_ssub_0Bits, 16, sizeof(DPair_with_ssub_0Bits), ARM_DPair_with_ssub_0RegClassID, 16, 16, 1, 1 }, 2212 { "QPR", QPR, QPRBits, 16, sizeof(QPRBits), ARM_QPRRegClassID, 16, 16, 1, 1 }, 2213 { "DPair_with_ssub_2", DPair_with_ssub_2, DPair_with_ssub_2Bits, 15, sizeof(DPair_with_ssub_2Bits), ARM_DPair_with_ssub_2RegClassID, 16, 16, 1, 1 }, 2214 { "DPair_with_dsub_0_in_DPR_8", DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM_DPair_with_dsub_0_in_DPR_8RegClassID, 16, 16, 1, 1 }, 2215 { "QPR_VFP2", QPR_VFP2, QPR_VFP2Bits, 8, sizeof(QPR_VFP2Bits), ARM_QPR_VFP2RegClassID, 16, 16, 1, 1 }, 2216 { "DPair_with_dsub_1_in_DPR_8", DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM_DPair_with_dsub_1_in_DPR_8RegClassID, 16, 16, 1, 1 }, 2217 { "QPR_8", QPR_8, QPR_8Bits, 4, sizeof(QPR_8Bits), ARM_QPR_8RegClassID, 16, 16, 1, 1 }, 2218 { "DTriple", DTriple, DTripleBits, 30, sizeof(DTripleBits), ARM_DTripleRegClassID, 24, 8, 1, 1 }, 2219 { "DTripleSpc", DTripleSpc, DTripleSpcBits, 28, sizeof(DTripleSpcBits), ARM_DTripleSpcRegClassID, 24, 8, 1, 1 }, 2220 { "DTripleSpc_with_ssub_0", DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM_DTripleSpc_with_ssub_0RegClassID, 24, 8, 1, 1 }, 2221 { "DTriple_with_ssub_0", DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 16, sizeof(DTriple_with_ssub_0Bits), ARM_DTriple_with_ssub_0RegClassID, 24, 8, 1, 1 }, 2222 { "DTriple_with_dsub_1_dsub_2_in_QPR", DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_1_dsub_2_in_QPRBits, 15, sizeof(DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, 2223 { "DTriple_with_qsub_0_in_QPR", DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, 2224 { "DTriple_with_ssub_2", DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 15, sizeof(DTriple_with_ssub_2Bits), ARM_DTriple_with_ssub_2RegClassID, 24, 8, 1, 1 }, 2225 { "DTripleSpc_with_dsub_2_then_ssub_0", DTripleSpc_with_dsub_2_then_ssub_0, DTripleSpc_with_dsub_2_then_ssub_0Bits, 14, sizeof(DTripleSpc_with_dsub_2_then_ssub_0Bits), ARM_DTripleSpc_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 }, 2226 { "DTriple_with_dsub_2_then_ssub_0", DTriple_with_dsub_2_then_ssub_0, DTriple_with_dsub_2_then_ssub_0Bits, 14, sizeof(DTriple_with_dsub_2_then_ssub_0Bits), ARM_DTriple_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 }, 2227 { "DTripleSpc_with_dsub_4_then_ssub_0", DTripleSpc_with_dsub_4_then_ssub_0, DTripleSpc_with_dsub_4_then_ssub_0Bits, 12, sizeof(DTripleSpc_with_dsub_4_then_ssub_0Bits), ARM_DTripleSpc_with_dsub_4_then_ssub_0RegClassID, 24, 8, 1, 1 }, 2228 { "DTripleSpc_with_dsub_0_in_DPR_8", DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 }, 2229 { "DTriple_with_dsub_0_in_DPR_8", DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM_DTriple_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 }, 2230 { "DTriple_with_qsub_0_in_QPR_VFP2", DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 24, 8, 1, 1 }, 2231 { "DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR", DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, 2232 { "DTriple_with_dsub_1_dsub_2_in_QPR_VFP2", DTriple_with_dsub_1_dsub_2_in_QPR_VFP2, DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 7, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM_DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 24, 8, 1, 1 }, 2233 { "DTriple_with_dsub_1_in_DPR_8", DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM_DTriple_with_dsub_1_in_DPR_8RegClassID, 24, 8, 1, 1 }, 2234 { "DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR", DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits, 7, sizeof(DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, 2235 { "DTripleSpc_with_dsub_2_in_DPR_8", DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 }, 2236 { "DTriple_with_dsub_2_in_DPR_8", DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM_DTriple_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 }, 2237 { "DTripleSpc_with_dsub_4_in_DPR_8", DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 24, 8, 1, 1 }, 2238 { "DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR", DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, 2239 { "DTriple_with_qsub_0_in_QPR_8", DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM_DTriple_with_qsub_0_in_QPR_8RegClassID, 24, 8, 1, 1 }, 2240 { "DTriple_with_dsub_1_dsub_2_in_QPR_8", DTriple_with_dsub_1_dsub_2_in_QPR_8, DTriple_with_dsub_1_dsub_2_in_QPR_8Bits, 3, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_8Bits), ARM_DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID, 24, 8, 1, 1 }, 2241 { "DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR", DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, 2242 { "DQuadSpc", DQuadSpc, DQuadSpcBits, 28, sizeof(DQuadSpcBits), ARM_DQuadSpcRegClassID, 32, 8, 1, 1 }, 2243 { "DQuadSpc_with_ssub_0", DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM_DQuadSpc_with_ssub_0RegClassID, 32, 8, 1, 1 }, 2244 { "DQuadSpc_with_dsub_2_then_ssub_0", DQuadSpc_with_dsub_2_then_ssub_0, DQuadSpc_with_dsub_2_then_ssub_0Bits, 14, sizeof(DQuadSpc_with_dsub_2_then_ssub_0Bits), ARM_DQuadSpc_with_dsub_2_then_ssub_0RegClassID, 32, 8, 1, 1 }, 2245 { "DQuadSpc_with_dsub_4_then_ssub_0", DQuadSpc_with_dsub_4_then_ssub_0, DQuadSpc_with_dsub_4_then_ssub_0Bits, 12, sizeof(DQuadSpc_with_dsub_4_then_ssub_0Bits), ARM_DQuadSpc_with_dsub_4_then_ssub_0RegClassID, 32, 8, 1, 1 }, 2246 { "DQuadSpc_with_dsub_0_in_DPR_8", DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 32, 8, 1, 1 }, 2247 { "DQuadSpc_with_dsub_2_in_DPR_8", DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 32, 8, 1, 1 }, 2248 { "DQuadSpc_with_dsub_4_in_DPR_8", DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 32, 8, 1, 1 }, 2249 { "DQuad", DQuad, DQuadBits, 29, sizeof(DQuadBits), ARM_DQuadRegClassID, 32, 32, 1, 1 }, 2250 { "DQuad_with_ssub_0", DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 16, sizeof(DQuad_with_ssub_0Bits), ARM_DQuad_with_ssub_0RegClassID, 32, 32, 1, 1 }, 2251 { "DQuad_with_ssub_2", DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 15, sizeof(DQuad_with_ssub_2Bits), ARM_DQuad_with_ssub_2RegClassID, 32, 32, 1, 1 }, 2252 { "QQPR", QQPR, QQPRBits, 15, sizeof(QQPRBits), ARM_QQPRRegClassID, 32, 32, 1, 1 }, 2253 { "DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_1_dsub_2_in_QPRBits, 14, sizeof(DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, 2254 { "DQuad_with_dsub_2_then_ssub_0", DQuad_with_dsub_2_then_ssub_0, DQuad_with_dsub_2_then_ssub_0Bits, 14, sizeof(DQuad_with_dsub_2_then_ssub_0Bits), ARM_DQuad_with_dsub_2_then_ssub_0RegClassID, 32, 32, 1, 1 }, 2255 { "DQuad_with_dsub_3_then_ssub_0", DQuad_with_dsub_3_then_ssub_0, DQuad_with_dsub_3_then_ssub_0Bits, 13, sizeof(DQuad_with_dsub_3_then_ssub_0Bits), ARM_DQuad_with_dsub_3_then_ssub_0RegClassID, 32, 32, 1, 1 }, 2256 { "DQuad_with_dsub_0_in_DPR_8", DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM_DQuad_with_dsub_0_in_DPR_8RegClassID, 32, 32, 1, 1 }, 2257 { "DQuad_with_qsub_0_in_QPR_VFP2", DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, 2258 { "DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, 2259 { "DQuad_with_dsub_1_dsub_2_in_QPR_VFP2", DQuad_with_dsub_1_dsub_2_in_QPR_VFP2, DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 7, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM_DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, 2260 { "DQuad_with_dsub_1_in_DPR_8", DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM_DQuad_with_dsub_1_in_DPR_8RegClassID, 32, 32, 1, 1 }, 2261 { "DQuad_with_qsub_1_in_QPR_VFP2", DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, 2262 { "DQuad_with_dsub_2_in_DPR_8", DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM_DQuad_with_dsub_2_in_DPR_8RegClassID, 32, 32, 1, 1 }, 2263 { "DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 6, sizeof(DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, 2264 { "DQuad_with_dsub_3_in_DPR_8", DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM_DQuad_with_dsub_3_in_DPR_8RegClassID, 32, 32, 1, 1 }, 2265 { "DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, 2266 { "DQuad_with_qsub_0_in_QPR_8", DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM_DQuad_with_qsub_0_in_QPR_8RegClassID, 32, 32, 1, 1 }, 2267 { "DQuad_with_dsub_1_dsub_2_in_QPR_8", DQuad_with_dsub_1_dsub_2_in_QPR_8, DQuad_with_dsub_1_dsub_2_in_QPR_8Bits, 3, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_8Bits), ARM_DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID, 32, 32, 1, 1 }, 2268 { "DQuad_with_qsub_1_in_QPR_8", DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM_DQuad_with_qsub_1_in_QPR_8RegClassID, 32, 32, 1, 1 }, 2269 { "DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, 2270 { "QQQQPR", QQQQPR, QQQQPRBits, 13, sizeof(QQQQPRBits), ARM_QQQQPRRegClassID, 64, 32, 1, 1 }, 2271 { "QQQQPR_with_ssub_0", QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM_QQQQPR_with_ssub_0RegClassID, 64, 32, 1, 1 }, 2272 { "QQQQPR_with_dsub_2_then_ssub_0", QQQQPR_with_dsub_2_then_ssub_0, QQQQPR_with_dsub_2_then_ssub_0Bits, 7, sizeof(QQQQPR_with_dsub_2_then_ssub_0Bits), ARM_QQQQPR_with_dsub_2_then_ssub_0RegClassID, 64, 32, 1, 1 }, 2273 { "QQQQPR_with_dsub_5_then_ssub_0", QQQQPR_with_dsub_5_then_ssub_0, QQQQPR_with_dsub_5_then_ssub_0Bits, 6, sizeof(QQQQPR_with_dsub_5_then_ssub_0Bits), ARM_QQQQPR_with_dsub_5_then_ssub_0RegClassID, 64, 32, 1, 1 }, 2274 { "QQQQPR_with_dsub_7_then_ssub_0", QQQQPR_with_dsub_7_then_ssub_0, QQQQPR_with_dsub_7_then_ssub_0Bits, 5, sizeof(QQQQPR_with_dsub_7_then_ssub_0Bits), ARM_QQQQPR_with_dsub_7_then_ssub_0RegClassID, 64, 32, 1, 1 }, 2275 { "QQQQPR_with_dsub_0_in_DPR_8", QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID, 64, 32, 1, 1 }, 2276 { "QQQQPR_with_dsub_2_in_DPR_8", QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID, 64, 32, 1, 1 }, 2277 { "QQQQPR_with_dsub_4_in_DPR_8", QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID, 64, 32, 1, 1 }, 2278 { "QQQQPR_with_dsub_6_in_DPR_8", QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID, 64, 32, 1, 1 }, 2279}; 2280 2281#endif // GET_REGINFO_MC_DESC 2282