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Searched refs:RESULT (Results 1 – 25 of 223) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/
Dctlz.ll12 ; CHECK: cpi [[RESULT:r[0-9]+]], 0
15 ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
17 ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
18 ; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
19 ; CHECK: lsr {{.*}}[[RESULT]]
20 ; CHECK: lsr {{.*}}[[RESULT]]
21 ; CHECK: or {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
27 ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
29 ; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
[all …]
Dcttz.ll12 ; CHECK: cpi [[RESULT:r[0-9]+]], 0
14 ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
16 ; CHECK: com {{.*}}[[RESULT]]
17 ; CHECK: and {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
18 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
21 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
24 ; CHECK: lsr {{.*}}[[RESULT]]
25 ; CHECK: lsr {{.*}}[[RESULT]]
26 ; CHECK: andi {{.*}}[[RESULT]], 51
[all …]
Dctpop.ll12 ; CHECK: mov [[SCRATCH:r[0-9]+]], [[RESULT:r[0-9]+]]
15 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
16 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
18 ; CHECK: lsr {{.*}}[[RESULT]]
19 ; CHECK: lsr {{.*}}[[RESULT]]
20 ; CHECK: andi {{.*}}[[RESULT]], 51
21 ; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
27 ; CHECK: add {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
29 ; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dicmp-with-zero.ll107 ; CHECK: mov [[RESULT:.*]],0x0
108 ; CHECK-NEXT: cmp [[RESULT]],0x0
110 ; OPTM1: mov [[RESULT:.*]],0x0
111 ; OPTM1-NEXT: cmp [[RESULT]],0x0
128 ; CHECK: mov [[RESULT:.*]],0x1
129 ; CHECK-NEXT: cmp [[RESULT]],0x0
131 ; OPTM1: mov [[RESULT:.*]],0x1
132 ; OPTM1-NEXT: cmp [[RESULT]],0x0
150 ; CHECK: mov [[RESULT:.*]],0x0
151 ; CHECK-NEXT: cmp [[RESULT]],0x0
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.rcp.ll18 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
19 ; SI-NOT: [[RESULT]]
20 ; SI: buffer_store_dword [[RESULT]]
28 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
29 ; SI-NOT: [[RESULT]]
30 ; SI: buffer_store_dword [[RESULT]]
65 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
66 ; SI-NOT: [[RESULT]]
67 ; SI: buffer_store_dwordx2 [[RESULT]]
75 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
[all …]
Dcttz_zero_undef.ll15 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
16 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
25 ; SI: v_ffbl_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
26 ; SI: buffer_store_dword [[RESULT]],
28 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
29 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
43 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
44 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
45 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
61 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
[all …]
Dsetcc-opt.ll8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
9 ; GCN-NEXT:buffer_store_byte [[RESULT]]
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
26 ; GCN-NEXT: buffer_store_byte [[RESULT]]
42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
43 ; GCN-NEXT: buffer_store_byte [[RESULT]]
56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
57 ; GCN-NEXT: buffer_store_byte [[RESULT]]
70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
71 ; GCN-NEXT: buffer_store_byte [[RESULT]]
[all …]
Dtrunc-cmp-constant.ll24 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
25 ; SI: buffer_store_byte [[RESULT]]
35 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
36 ; SI: buffer_store_byte [[RESULT]]
47 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
48 ; SI: buffer_store_byte [[RESULT]]
59 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
60 ; SI: buffer_store_byte [[RESULT]]
70 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
71 ; SI: buffer_store_byte [[RESULT]]
[all …]
Dctpop.ll28 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
29 ; GCN: buffer_store_dword [[RESULT]],
44 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
45 ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
46 ; GCN: buffer_store_dword [[RESULT]],
64 ; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
65 ; GCN: buffer_store_dword [[RESULT]],
177 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
178 ; GCN: buffer_store_dword [[RESULT]],
192 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
[all …]
Dllvm.amdgcn.class.ll14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
15 ; SI-NEXT: buffer_store_dword [[RESULT]]
29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
30 ; SI-NEXT: buffer_store_dword [[RESULT]]
45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
46 ; SI-NEXT: buffer_store_dword [[RESULT]]
61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
62 ; SI-NEXT: buffer_store_dword [[RESULT]]
76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
77 ; SI-NEXT: buffer_store_dword [[RESULT]]
[all …]
Dllvm.AMDGPU.clamp.ll10 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
11 ; SI: buffer_store_dword [[RESULT]]
23 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
24 ; SI: buffer_store_dword [[RESULT]]
35 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
36 ; SI: buffer_store_dword [[RESULT]]
47 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
48 ; SI: buffer_store_dword [[RESULT]]
Duse-sgpr-multiple-times.ll12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
13 ; GCN: buffer_store_dword [[RESULT]]
22 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
23 ; GCN: buffer_store_dword [[RESULT]]
36 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
37 ; GCN: buffer_store_dword [[RESULT]]
76 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
77 ; GCN: buffer_store_dword [[RESULT]]
90 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
91 ; GCN: buffer_store_dword [[RESULT]]
[all …]
Dfract.ll12 ; GCN-SAFE: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
14 ; GCN-UNSAFE: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
16 ; GCN: buffer_store_dword [[RESULT]]
27 ; GCN-SAFE: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT]], [[FLR]]
29 ; GCN-UNSAFE: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]]
31 ; GCN: buffer_store_dword [[RESULT]]
43 ; GCN-SAFE: v_sub_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT]]|, [[FLR]]
45 ; GCN-UNSAFE: v_fract_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT:v[0-9]+]]|
47 ; GCN: buffer_store_dword [[RESULT]]
Dshl_add_constant.ll9 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 36, [[REG]]
10 ; SI: buffer_store_dword [[RESULT]]
43 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xf9c, [[REG]]
44 ; SI: buffer_store_dword [[RESULT]]
60 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], [[Y]]
61 ; SI: s_addk_i32 [[RESULT]], 0x3d8
62 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
77 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
78 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfmuladd.f32.ll79 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
82 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
84 ; SI-DENORM buffer_store_dword [[RESULT]]
85 ; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
110 ; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
113 ; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
115 ; SI-DENORM: buffer_store_dword [[RESULT]]
116 ; VI-DENORM: {{global|flat}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
140 ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
143 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
[all …]
Dllvm.amdgcn.rcp.ll36 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
37 ; SI-NOT: [[RESULT]]
38 ; SI: buffer_store_dword [[RESULT]]
46 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
47 ; SI-NOT: [[RESULT]]
48 ; SI: buffer_store_dword [[RESULT]]
83 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
84 ; SI-NOT: [[RESULT]]
85 ; SI: buffer_store_dwordx2 [[RESULT]]
93 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
[all …]
Dtrunc-cmp-constant.ll26 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
27 ; SI: buffer_store_byte [[RESULT]]
37 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
38 ; SI: buffer_store_byte [[RESULT]]
49 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
50 ; SI: buffer_store_byte [[RESULT]]
61 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
62 ; SI: buffer_store_byte [[RESULT]]
72 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
73 ; SI: buffer_store_byte [[RESULT]]
[all …]
Dsetcc-opt.ll8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
9 ; GCN-NEXT:buffer_store_byte [[RESULT]]
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
26 ; GCN-NEXT: buffer_store_byte [[RESULT]]
42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
43 ; GCN-NEXT: buffer_store_byte [[RESULT]]
56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
57 ; GCN-NEXT: buffer_store_byte [[RESULT]]
70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
71 ; GCN-NEXT: buffer_store_byte [[RESULT]]
[all …]
Dfmuladd.f16.ll31 ; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
32 ; VI-DENORM: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
53 ; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
54 ; VI-DENORM: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
75 ; VI-DENORM-CONTRACT: v_fma_f16 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
78 ; VI-DENORM-STRICT: v_add_f16_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
80 ; VI-DENORM: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
104 ; VI-DENORM-CONTRACT: v_fma_f16 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
107 ; VI-DENORM-STRICT: v_add_f16_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
109 ; VI-DENORM: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
[all …]
Dconstant-fold-mi-operands.ll5 ; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
6 ; GCN-NOT: [[RESULT]]
7 ; GCN: buffer_store_dword [[RESULT]]
17 ; GCN: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
18 ; GCN-NOT: [[RESULT]]
19 ; GCN: buffer_store_dword [[RESULT]]
28 ; GCN: v_mbcnt_lo_u32_b32{{(_e64)*}} [[RESULT:v[0-9]+]]
29 ; GCN-NOT: [[RESULT]]
30 ; GCN: buffer_store_dword [[RESULT]]
53 ; GCN: v_mbcnt_lo_u32_b32{{(_e64)*}} [[RESULT:v[0-9]+]]
[all …]
Dfdiv.f16.ll33 ; GFX8_9: v_div_fixup_f16 [[RESULT:v[0-9]+]], [[CVT_BACK]], [[RHS]], [[LHS]]
34 ; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
55 ; GFX8_9: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
56 ; GFX8_9-NOT: [[RESULT]]
57 ; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
73 ; GFX8_9: v_rcp_f16_e64 [[RESULT:v[0-9]+]], |[[VAL]]|
74 ; GFX8_9-NOT: [RESULT]]
75 ; GFX8_9: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
92 ; GFX8_9: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
93 ; GFX8_9-NOT: [[RESULT]]
[all …]
Duse-sgpr-multiple-times.ll12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
13 ; GCN: buffer_store_dword [[RESULT]]
22 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
23 ; GCN: buffer_store_dword [[RESULT]]
34 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], s[[SGPR0]], [[VGPR1]]
35 ; GCN: buffer_store_dword [[RESULT]]
74 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], [[VGPR1]], s[[SGPR0]]
75 ; GCN: buffer_store_dword [[RESULT]]
86 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], s[[SGPR0]], s[[SGPR0]]
87 ; GCN: buffer_store_dword [[RESULT]]
[all …]
Dfmin3.ll9 ; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
10 ; GCN: buffer_store_dword [[RESULT]],
26 ; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
27 ; GCN: buffer_store_dword [[RESULT]],
44 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
47 ; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
49 ; GFX9: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
50 ; GCN: buffer_store_short [[RESULT]],
71 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]]
74 ; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
[all …]
Dllvm.amdgcn.class.ll14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
15 ; SI-NEXT: buffer_store_dword [[RESULT]]
29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
30 ; SI-NEXT: buffer_store_dword [[RESULT]]
45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
46 ; SI-NEXT: buffer_store_dword [[RESULT]]
61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
62 ; SI-NEXT: buffer_store_dword [[RESULT]]
76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
77 ; SI-NEXT: buffer_store_dword [[RESULT]]
[all …]
/external/toolchain-utils/crosperf/test_cache/test_input/
Dresults.txt1 …RESULT 3d-cube: 3d-cube= [28,28,28,28,31,26,28,28,28,27] ms\n13:23:35 INFO | autoserv| Avg 3d-cube…

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