| /external/llvm/test/CodeGen/AArch64/ |
| D | divrem.ll | 3 ; SDIVREM/UDIVREM DAG nodes are generated but expanded when lowering and
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | divrem.ll | 3 ; SDIVREM/UDIVREM DAG nodes are generated but expanded when lowering and
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 198 SDIVREM, UDIVREM, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 204 SDIVREM, UDIVREM, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 210 SDIVREM, UDIVREM, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 81 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in BlackfinTargetLowering()
82 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in BlackfinTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 155 setOperationAction(ISD::SDIVREM, VT, Custom); in AVRTargetLowering()
333 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
335 bool IsSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
697 case ISD::SDIVREM: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 93 SDIVREM, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 157 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
163 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 186 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 269 case ISD::SDIVREM: in LegalizeOp()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 184 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); in SPUTargetLowering()
190 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in SPUTargetLowering()
196 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SPUTargetLowering()
202 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SPUTargetLowering()
208 setOperationAction(ISD::SDIVREM, MVT::i128, Expand); in SPUTargetLowering()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 150 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
156 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 198 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
205 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
233 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
280 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
456 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 80 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 219 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 98 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 603 case ISD::SDIVREM: { in Select()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 131 setOperationAction(ISD::SDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
137 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 87 setOperationAction(ISD::SDIVREM, VT, Expand); in BPFTargetLowering()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 300 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
385 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
711 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
1551 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 219 setTargetDAGCombine(ISD::SDIVREM); in MipsTargetLowering()
424 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : in PerformDivRemCombine()
648 case ISD::SDIVREM: in PerformDAGCombine()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 110 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1960 case ISD::SDIVREM: in Select()
1965 bool isSigned = Opcode == ISD::SDIVREM; in Select()
|