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Searched refs:SOCFPGA_RESET (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dreset_manager_s10.c49 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); in socfpga_per_reset_all()
107 reset_emac = SOCFPGA_RESET(EMAC0); in socfpga_emac_manage_reset()
108 reset_emacocp = SOCFPGA_RESET(EMAC0_OCP); in socfpga_emac_manage_reset()
111 reset_emac = SOCFPGA_RESET(EMAC1); in socfpga_emac_manage_reset()
112 reset_emacocp = SOCFPGA_RESET(EMAC1_OCP); in socfpga_emac_manage_reset()
115 reset_emac = SOCFPGA_RESET(EMAC2); in socfpga_emac_manage_reset()
116 reset_emacocp = SOCFPGA_RESET(EMAC2_OCP); in socfpga_emac_manage_reset()
Dspl.c52 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in spl_boot_device()
56 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); in spl_boot_device()
57 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device()
61 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); in spl_boot_device()
118 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); in board_init_f()
119 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); in board_init_f()
120 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); in board_init_f()
Dmisc_gen5.c47 reset = SOCFPGA_RESET(EMAC0); in gen5_dwmac_reset()
50 reset = SOCFPGA_RESET(EMAC1); in gen5_dwmac_reset()
68 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); in socfpga_eth_reset()
69 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); in socfpga_eth_reset()
216 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); in arch_early_init_r()
217 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); in arch_early_init_r()
221 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in arch_early_init_r()
Dmisc_arria10.c49 reset = SOCFPGA_RESET(EMAC0); in arria10_dwmac_reset()
51 reset = SOCFPGA_RESET(EMAC1); in arria10_dwmac_reset()
53 reset = SOCFPGA_RESET(EMAC2); in arria10_dwmac_reset()
70 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); in socfpga_eth_reset()
71 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); in socfpga_eth_reset()
72 socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1); in socfpga_eth_reset()
Dreset_manager_arria10.c37 socfpga_per_reset(SOCFPGA_RESET(UART1), assert); in socfpga_reset_uart()
39 socfpga_per_reset(SOCFPGA_RESET(UART0), assert); in socfpga_reset_uart()
299 const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | in socfpga_per_reset_all()
300 (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0)))); in socfpga_per_reset_all()
Dmisc.c136 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); in arch_cpu_init()
137 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); in arch_cpu_init()
Dreset_manager_gen5.c58 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); in socfpga_per_reset_all()
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dreset_manager.h39 #define SOCFPGA_RESET(_name) RSTMGR_##_name macro
Dreset_manager_s10.h114 #define SOCFPGA_RESET(_name) RSTMGR_##_name macro