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Searched refs:Src0RC (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1242 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1243 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1244 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1249 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1262 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1267 (ins Src0RC:$src0, clampmod:$clamp),
1268 (ins Src0RC:$src0))
1274 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1277 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1283 (ins Src0RC:$src0, Src1RC:$src1, clampmod:$clamp),
[all …]
DSIFixSGPRCopies.cpp696 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
698 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
701 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
DSIInstrInfo.cpp3581 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
3582 if (DstRC != Src0RC) { in legalizeOperands()
4189 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
4193 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
4195 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
4205 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
4247 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg()); in splitScalar64BitAddSub() local
4249 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
4252 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub()
4258 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp356 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
358 Src0RC = MRI.getRegClass(MI.getOperand(1).getReg()); in runOnMachineFunction()
361 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
DSIInstrInfo.td1189 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1190 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1191 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1196 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1208 (ins FPInputMods:$src0_modifiers, Src0RC:$src0,
1212 (ins Src0RC:$src0)
1217 (ins FPInputMods:$src0_modifiers, Src0RC:$src0,
1222 (ins Src0RC:$src0, Src1RC:$src1)
1227 (ins FPInputMods:$src0_modifiers, Src0RC:$src0,
1233 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
[all …]
DSIInstrInfo.cpp2314 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
2315 if (DstRC != Src0RC) { in legalizeOperands()
2709 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
2713 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
2715 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
2726 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
2763 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitBinaryOp() local
2767 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
2774 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp()
2788 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp()