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Searched refs:VORN (Results 1 – 16 of 16) sorted by relevance

/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt4237 VORN/VORNQ output:
4238 VORN/VORNQ:0:result_int8x8 [] = { fffffffd, fffffffd, ffffffff, ffffffff, fffffffd, fffffffd, fffff…
4239 VORN/VORNQ:1:result_int16x4 [] = { fffffff3, fffffff3, fffffff3, fffffff3, }
4240 VORN/VORNQ:2:result_int32x2 [] = { fffffffc, fffffffd, }
4241 VORN/VORNQ:3:result_int64x1 [] = { fffffffffffffffb, }
4242 VORN/VORNQ:4:result_uint8x8 [] = { fb, fb, fb, fb, ff, ff, ff, ff, }
4243 VORN/VORNQ:5:result_uint16x4 [] = { fff1, fff1, fff3, fff3, }
4244 VORN/VORNQ:6:result_uint32x2 [] = { fffffff7, fffffff7, }
4245 VORN/VORNQ:7:result_uint64x1 [] = { fffffffffffffffd, }
4246 VORN/VORNQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
Dref-rvct-neon.txt4771 VORN/VORNQ output:
4772 VORN/VORNQ:0:result_int8x8 [] = { fffffffd, fffffffd, ffffffff, ffffffff, fffffffd, fffffffd, fffff…
4773 VORN/VORNQ:1:result_int16x4 [] = { fffffff3, fffffff3, fffffff3, fffffff3, }
4774 VORN/VORNQ:2:result_int32x2 [] = { fffffffc, fffffffd, }
4775 VORN/VORNQ:3:result_int64x1 [] = { fffffffffffffffb, }
4776 VORN/VORNQ:4:result_uint8x8 [] = { fb, fb, fb, fb, ff, ff, ff, ff, }
4777 VORN/VORNQ:5:result_uint16x4 [] = { fff1, fff1, fff3, fff3, }
4778 VORN/VORNQ:6:result_uint32x2 [] = { fffffff7, fffffff7, }
4779 VORN/VORNQ:7:result_uint64x1 [] = { fffffffffffffffd, }
4780 VORN/VORNQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
Dref-rvct-all.txt4771 VORN/VORNQ output:
4772 VORN/VORNQ:0:result_int8x8 [] = { fffffffd, fffffffd, ffffffff, ffffffff, fffffffd, fffffffd, fffff…
4773 VORN/VORNQ:1:result_int16x4 [] = { fffffff3, fffffff3, fffffff3, fffffff3, }
4774 VORN/VORNQ:2:result_int32x2 [] = { fffffffc, fffffffd, }
4775 VORN/VORNQ:3:result_int64x1 [] = { fffffffffffffffb, }
4776 VORN/VORNQ:4:result_uint8x8 [] = { fb, fb, fb, fb, ff, ff, ff, ff, }
4777 VORN/VORNQ:5:result_uint16x4 [] = { fff1, fff1, fff3, fff3, }
4778 VORN/VORNQ:6:result_uint32x2 [] = { fffffff7, fffffff7, }
4779 VORN/VORNQ:7:result_uint64x1 [] = { fffffffffffffffd, }
4780 VORN/VORNQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
Dexpected_input4gcc-nofp16.txt4262 VORN/VORNQ output:
Dexpected_input4gcc.txt4580 VORN/VORNQ output:
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleSwift.td561 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
DARMScheduleR52.td815 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F1], (instregex "VORR", "VORN", "VREV")>;
DARMScheduleA57.td1013 (instregex "VAND", "VBIC", "VMVN", "VORR", "VORN", "VEOR")>;
DARMScheduleA9.td2426 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
DARMInstrNEON.td5226 // VORN : Vector Bitwise OR NOT
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td544 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
DARMScheduleA9.td2402 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
DARMInstrNEON.td4952 // VORN : Vector Bitwise OR NOT
/external/v8/src/arm/
Dassembler-arm.cc4192 enum BinaryBitwiseOp { VAND, VBIC, VBIF, VBIT, VBSL, VEOR, VORR, VORN }; enumerator
4217 case VORN: in EncodeNeonBinaryBitwiseOp()
/external/clang/include/clang/Basic/
Darm_neon.td806 def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td3828 // VORN : Vector Bitwise OR NOT