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Searched refs:XCHAL_DCACHE_LINEWIDTH (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/xtensa/include/asm/
Dcacheasm.h17 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
84 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
102 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
111 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
121 XCHAL_DCACHE_LINEWIDTH
141 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
150 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
159 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
178 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
187 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
[all …]
/external/u-boot/arch/xtensa/include/asm/arch-dc232b/
Dcore.h122 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/external/u-boot/arch/xtensa/include/asm/arch-dc233c/
Dcore.h141 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/external/u-boot/arch/xtensa/include/asm/arch-de212/
Dcore.h189 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro