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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Xtensa processor core configuration information.
4  * This file is autogenerated, please do not edit.
5  *
6  * Copyright (C) 1999-2010 Tensilica Inc.
7  */
8 
9 #ifndef _XTENSA_CORE_CONFIGURATION_H
10 #define _XTENSA_CORE_CONFIGURATION_H
11 
12 
13 /****************************************************************************
14 	    Parameters Useful for Any Code, USER or PRIVILEGED
15  ****************************************************************************/
16 
17 /*
18  *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
19  *  configured, and a value of 0 otherwise.  These macros are always defined.
20  */
21 
22 
23 /*----------------------------------------------------------------------
24 				ISA
25   ----------------------------------------------------------------------*/
26 
27 #define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
28 #define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
29 #define XCHAL_NUM_AREGS			32	/* num of physical addr regs */
30 #define XCHAL_NUM_AREGS_LOG2		5	/* log2(XCHAL_NUM_AREGS) */
31 #define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
32 #define XCHAL_HAVE_DEBUG		1	/* debug option */
33 #define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
34 #define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
35 #define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
36 #define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
37 #define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
38 #define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
39 #define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
40 #define XCHAL_HAVE_MUL32		1	/* MULL instruction */
41 #define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
42 #define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
43 #define XCHAL_HAVE_L32R			1	/* L32R instruction */
44 #define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
45 #define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
46 #define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
47 #define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
48 #define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
49 #define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
50 #define XCHAL_HAVE_ABS			1	/* ABS instruction */
51 /*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
52 /*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
53 #define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
54 #define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
55 #define XCHAL_HAVE_SPECULATION		0	/* speculation */
56 #define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
57 #define XCHAL_NUM_CONTEXTS		1	/* */
58 #define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
59 #define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
60 #define XCHAL_HAVE_PRID			1	/* processor ID register */
61 #define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
62 #define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
63 #define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
64 #define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
65 #define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
66 #define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
67 #define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
68 #define XCHAL_HAVE_MAC16		1	/* MAC16 package */
69 #define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
70 #define XCHAL_HAVE_FP			0	/* floating point pkg */
71 #define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
72 #define XCHAL_HAVE_DFP_accel		0	/* double precision FP acceleration pkg */
73 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
74 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
75 #define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
76 #define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
77 #define XCHAL_HAVE_HIFI2EP	0	/* HiFi2EP */
78 #define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
79 #define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
80 #define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
81 #define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
82 #define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
83 #define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
84 #define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
85 #define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
86 #define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
87 #define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
88 
89 
90 /*----------------------------------------------------------------------
91 				MISC
92   ----------------------------------------------------------------------*/
93 
94 #define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */
95 #define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
96 #define XCHAL_DATA_WIDTH		4	/* data width in bytes */
97 /*  In T1050, applies to selected core load and store instructions (see ISA): */
98 #define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
99 #define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
100 #define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
101 #define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
102 
103 #define XCHAL_SW_VERSION		900001	/* sw version of this header */
104 
105 #define XCHAL_CORE_ID			"dc233c"	/* alphanum core name
106 						   (CoreID) set in the Xtensa
107 						   Processor Generator */
108 
109 #define XCHAL_CORE_DESCRIPTION		"dc233c"
110 #define XCHAL_BUILD_UNIQUE_ID		0x00004B21	/* 22-bit sw build ID */
111 
112 /*
113  *  These definitions describe the hardware targeted by this software.
114  */
115 #define XCHAL_HW_CONFIGID0		0xC56707FE	/* ConfigID hi 32 bits*/
116 #define XCHAL_HW_CONFIGID1		0x14404B21	/* ConfigID lo 32 bits*/
117 #define XCHAL_HW_VERSION_NAME		"LX4.0.1"	/* full version name */
118 #define XCHAL_HW_VERSION_MAJOR		2400	/* major ver# of targeted hw */
119 #define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
120 #define XCHAL_HW_VERSION		240001	/* major*100+minor */
121 #define XCHAL_HW_REL_LX4		1
122 #define XCHAL_HW_REL_LX4_0		1
123 #define XCHAL_HW_REL_LX4_0_1		1
124 #define XCHAL_HW_CONFIGID_RELIABLE	1
125 /*  If software targets a *range* of hardware versions, these are the bounds: */
126 #define XCHAL_HW_MIN_VERSION_MAJOR	2400	/* major v of earliest tgt hw */
127 #define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
128 #define XCHAL_HW_MIN_VERSION		240001	/* earliest targeted hw */
129 #define XCHAL_HW_MAX_VERSION_MAJOR	2400	/* major v of latest tgt hw */
130 #define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
131 #define XCHAL_HW_MAX_VERSION		240001	/* latest targeted hw */
132 
133 
134 /*----------------------------------------------------------------------
135 				CACHE
136   ----------------------------------------------------------------------*/
137 
138 #define XCHAL_ICACHE_LINESIZE		32	/* I-cache line size in bytes */
139 #define XCHAL_DCACHE_LINESIZE		32	/* D-cache line size in bytes */
140 #define XCHAL_ICACHE_LINEWIDTH		5	/* log2(I line size in bytes) */
141 #define XCHAL_DCACHE_LINEWIDTH		5	/* log2(D line size in bytes) */
142 
143 #define XCHAL_ICACHE_SIZE		16384	/* I-cache size in bytes or 0 */
144 #define XCHAL_DCACHE_SIZE		16384	/* D-cache size in bytes or 0 */
145 
146 #define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
147 #define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
148 
149 #define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
150 
151 
152 
153 
154 /****************************************************************************
155     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
156  ****************************************************************************/
157 
158 
159 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
160 
161 /*----------------------------------------------------------------------
162 				CACHE
163   ----------------------------------------------------------------------*/
164 
165 #define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
166 
167 /*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
168 
169 /*  Number of cache sets in log2(lines per way):  */
170 #define XCHAL_ICACHE_SETWIDTH		7
171 #define XCHAL_DCACHE_SETWIDTH		7
172 
173 /*  Cache set associativity (number of ways):  */
174 #define XCHAL_ICACHE_WAYS		4
175 #define XCHAL_DCACHE_WAYS		4
176 
177 /*  Cache features:  */
178 #define XCHAL_ICACHE_LINE_LOCKABLE	1
179 #define XCHAL_DCACHE_LINE_LOCKABLE	1
180 #define XCHAL_ICACHE_ECC_PARITY		0
181 #define XCHAL_DCACHE_ECC_PARITY		0
182 
183 /*  Cache access size in bytes (affects operation of SICW instruction):  */
184 #define XCHAL_ICACHE_ACCESS_SIZE	4
185 #define XCHAL_DCACHE_ACCESS_SIZE	4
186 
187 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
188 #define XCHAL_CA_BITS			4
189 
190 
191 /*----------------------------------------------------------------------
192 			INTERNAL I/D RAM/ROMs and XLMI
193   ----------------------------------------------------------------------*/
194 
195 #define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
196 #define XCHAL_NUM_INSTRAM		0	/* number of core instr. RAMs */
197 #define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
198 #define XCHAL_NUM_DATARAM		0	/* number of core data RAMs */
199 #define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
200 #define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
201 
202 #define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
203 
204 
205 /*----------------------------------------------------------------------
206 			INTERRUPTS and TIMERS
207   ----------------------------------------------------------------------*/
208 
209 #define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
210 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
211 #define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
212 #define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
213 #define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
214 #define XCHAL_NUM_INTERRUPTS		22	/* number of interrupts */
215 #define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
216 #define XCHAL_NUM_EXTINTERRUPTS		17	/* num of external interrupts */
217 #define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
218 						   (not including level zero) */
219 #define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
220 	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
221 
222 /*  Masks of interrupts at each interrupt level:  */
223 #define XCHAL_INTLEVEL1_MASK		0x001F80FF
224 #define XCHAL_INTLEVEL2_MASK		0x00000100
225 #define XCHAL_INTLEVEL3_MASK		0x00200E00
226 #define XCHAL_INTLEVEL4_MASK		0x00001000
227 #define XCHAL_INTLEVEL5_MASK		0x00002000
228 #define XCHAL_INTLEVEL6_MASK		0x00000000
229 #define XCHAL_INTLEVEL7_MASK		0x00004000
230 
231 /*  Masks of interrupts at each range 1..n of interrupt levels:  */
232 #define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x001F80FF
233 #define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x001F81FF
234 #define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x003F8FFF
235 #define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x003F9FFF
236 #define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x003FBFFF
237 #define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x003FBFFF
238 #define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x003FFFFF
239 
240 /*  Level of each interrupt:  */
241 #define XCHAL_INT0_LEVEL		1
242 #define XCHAL_INT1_LEVEL		1
243 #define XCHAL_INT2_LEVEL		1
244 #define XCHAL_INT3_LEVEL		1
245 #define XCHAL_INT4_LEVEL		1
246 #define XCHAL_INT5_LEVEL		1
247 #define XCHAL_INT6_LEVEL		1
248 #define XCHAL_INT7_LEVEL		1
249 #define XCHAL_INT8_LEVEL		2
250 #define XCHAL_INT9_LEVEL		3
251 #define XCHAL_INT10_LEVEL		3
252 #define XCHAL_INT11_LEVEL		3
253 #define XCHAL_INT12_LEVEL		4
254 #define XCHAL_INT13_LEVEL		5
255 #define XCHAL_INT14_LEVEL		7
256 #define XCHAL_INT15_LEVEL		1
257 #define XCHAL_INT16_LEVEL		1
258 #define XCHAL_INT17_LEVEL		1
259 #define XCHAL_INT18_LEVEL		1
260 #define XCHAL_INT19_LEVEL		1
261 #define XCHAL_INT20_LEVEL		1
262 #define XCHAL_INT21_LEVEL		3
263 #define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
264 #define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
265 #define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
266 						   EXCSAVE/EPS/EPC_n, RFI n) */
267 
268 /*  Type of each interrupt:  */
269 #define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
270 #define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
271 #define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
272 #define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
273 #define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
274 #define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
275 #define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
276 #define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
277 #define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
278 #define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
279 #define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
280 #define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
281 #define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
282 #define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
283 #define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
284 #define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
285 #define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
286 #define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
287 #define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
288 #define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
289 #define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
290 #define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
291 
292 /*  Masks of interrupts for each type of interrupt:  */
293 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000
294 #define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000880
295 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x003F8000
296 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000133F
297 #define XCHAL_INTTYPE_MASK_TIMER	0x00002440
298 #define XCHAL_INTTYPE_MASK_NMI		0x00004000
299 #define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
300 
301 /*  Interrupt numbers assigned to specific interrupt sources:  */
302 #define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
303 #define XCHAL_TIMER1_INTERRUPT		10	/* CCOMPARE1 */
304 #define XCHAL_TIMER2_INTERRUPT		13	/* CCOMPARE2 */
305 #define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
306 #define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
307 
308 /*  Interrupt numbers for levels at which only one interrupt is configured:  */
309 #define XCHAL_INTLEVEL2_NUM		8
310 #define XCHAL_INTLEVEL4_NUM		12
311 #define XCHAL_INTLEVEL5_NUM		13
312 #define XCHAL_INTLEVEL7_NUM		14
313 /*  (There are many interrupts each at level(s) 1, 3.)  */
314 
315 
316 /*
317  *  External interrupt vectors/levels.
318  *  These macros describe how Xtensa processor interrupt numbers
319  *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
320  *  map to external BInterrupt<n> pins, for those interrupts
321  *  configured as external (level-triggered, edge-triggered, or NMI).
322  *  See the Xtensa processor databook for more details.
323  */
324 
325 /*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
326 #define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
327 #define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
328 #define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
329 #define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
330 #define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
331 #define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
332 #define XCHAL_EXTINT6_NUM		8	/* (intlevel 2) */
333 #define XCHAL_EXTINT7_NUM		9	/* (intlevel 3) */
334 #define XCHAL_EXTINT8_NUM		12	/* (intlevel 4) */
335 #define XCHAL_EXTINT9_NUM		14	/* (intlevel 7) */
336 #define XCHAL_EXTINT10_NUM		15	/* (intlevel 1) */
337 #define XCHAL_EXTINT11_NUM		16	/* (intlevel 1) */
338 #define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
339 #define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
340 #define XCHAL_EXTINT14_NUM		19	/* (intlevel 1) */
341 #define XCHAL_EXTINT15_NUM		20	/* (intlevel 1) */
342 #define XCHAL_EXTINT16_NUM		21	/* (intlevel 3) */
343 
344 
345 /*----------------------------------------------------------------------
346 			EXCEPTIONS and VECTORS
347   ----------------------------------------------------------------------*/
348 
349 #define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
350 						   number: 1 == XEA1 (old)
351 							   2 == XEA2 (new)
352 							   0 == XEAX (extern) or TX */
353 #define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
354 #define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
355 #define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
356 #define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
357 #define XCHAL_HAVE_HALT			0	/* halt architecture option */
358 #define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
359 #define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
360 #define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
361 #define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
362 #define XCHAL_VECBASE_RESET_VADDR	0x00002000  /* VECBASE reset value */
363 #define XCHAL_VECBASE_RESET_PADDR	0x00002000
364 #define XCHAL_RESET_VECBASE_OVERLAP	0
365 
366 #define XCHAL_RESET_VECTOR0_VADDR	0xFE000000
367 #define XCHAL_RESET_VECTOR0_PADDR	0xFE000000
368 #define XCHAL_RESET_VECTOR1_VADDR	0x00001000
369 #define XCHAL_RESET_VECTOR1_PADDR	0x00001000
370 #define XCHAL_RESET_VECTOR_VADDR	0xFE000000
371 #define XCHAL_RESET_VECTOR_PADDR	0xFE000000
372 #define XCHAL_USER_VECOFS		0x00000340
373 #define XCHAL_USER_VECTOR_VADDR		0x00002340
374 #define XCHAL_USER_VECTOR_PADDR		0x00002340
375 #define XCHAL_KERNEL_VECOFS		0x00000300
376 #define XCHAL_KERNEL_VECTOR_VADDR	0x00002300
377 #define XCHAL_KERNEL_VECTOR_PADDR	0x00002300
378 #define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
379 #define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x000023C0
380 #define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x000023C0
381 #define XCHAL_WINDOW_OF4_VECOFS		0x00000000
382 #define XCHAL_WINDOW_UF4_VECOFS		0x00000040
383 #define XCHAL_WINDOW_OF8_VECOFS		0x00000080
384 #define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
385 #define XCHAL_WINDOW_OF12_VECOFS	0x00000100
386 #define XCHAL_WINDOW_UF12_VECOFS	0x00000140
387 #define XCHAL_WINDOW_VECTORS_VADDR	0x00002000
388 #define XCHAL_WINDOW_VECTORS_PADDR	0x00002000
389 #define XCHAL_INTLEVEL2_VECOFS		0x00000180
390 #define XCHAL_INTLEVEL2_VECTOR_VADDR	0x00002180
391 #define XCHAL_INTLEVEL2_VECTOR_PADDR	0x00002180
392 #define XCHAL_INTLEVEL3_VECOFS		0x000001C0
393 #define XCHAL_INTLEVEL3_VECTOR_VADDR	0x000021C0
394 #define XCHAL_INTLEVEL3_VECTOR_PADDR	0x000021C0
395 #define XCHAL_INTLEVEL4_VECOFS		0x00000200
396 #define XCHAL_INTLEVEL4_VECTOR_VADDR	0x00002200
397 #define XCHAL_INTLEVEL4_VECTOR_PADDR	0x00002200
398 #define XCHAL_INTLEVEL5_VECOFS		0x00000240
399 #define XCHAL_INTLEVEL5_VECTOR_VADDR	0x00002240
400 #define XCHAL_INTLEVEL5_VECTOR_PADDR	0x00002240
401 #define XCHAL_INTLEVEL6_VECOFS		0x00000280
402 #define XCHAL_INTLEVEL6_VECTOR_VADDR	0x00002280
403 #define XCHAL_INTLEVEL6_VECTOR_PADDR	0x00002280
404 #define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
405 #define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
406 #define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
407 #define XCHAL_NMI_VECOFS		0x000002C0
408 #define XCHAL_NMI_VECTOR_VADDR		0x000022C0
409 #define XCHAL_NMI_VECTOR_PADDR		0x000022C0
410 #define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
411 #define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
412 #define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
413 
414 
415 /*----------------------------------------------------------------------
416 				DEBUG
417   ----------------------------------------------------------------------*/
418 
419 #define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
420 #define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
421 #define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
422 #define XCHAL_HAVE_OCD_DIR_ARRAY	1	/* faster OCD option */
423 
424 
425 /*----------------------------------------------------------------------
426 				MMU
427   ----------------------------------------------------------------------*/
428 
429 /*  See core-matmap.h header file for more details.  */
430 
431 #define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
432 #define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
433 #define XCHAL_SPANNING_WAY		6	/* TLB spanning way number */
434 #define XCHAL_HAVE_IDENTITY_MAP		0	/* vaddr == paddr always */
435 #define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
436 #define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
437 #define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
438 #define XCHAL_HAVE_PTP_MMU		1	/* full MMU (with page table
439 						   [autorefill] and protection)
440 						   usable for an MMU-based OS */
441 /*  If none of the above last 4 are set, it's a custom TLB configuration.  */
442 #define XCHAL_ITLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
443 #define XCHAL_DTLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
444 
445 #define XCHAL_MMU_ASID_BITS		8	/* number of bits in ASIDs */
446 #define XCHAL_MMU_RINGS			4	/* number of rings (1..4) */
447 #define XCHAL_MMU_RING_BITS		2	/* num of bits in RING field */
448 
449 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
450 
451 
452 #endif /* _XTENSA_CORE_CONFIGURATION_H */
453 
454