| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 20 TmpInst.addOperand(MCOp);
22 TmpInst.addOperand(MCOperand::createImm(14));
23 TmpInst.addOperand(MCOperand::createReg(0));
33 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp);
41 TmpInst.addOperand(MCOp);
44 TmpInst.addOperand(MCOp);
48 TmpInst.addOperand(MCOp);
58 TmpInst.addOperand(MCOp);
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 20 TmpInst.addOperand(MCOp);
23 TmpInst.addOperand(MCOp);
26 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp);
42 TmpInst.addOperand(MCOp);
52 TmpInst.addOperand(MCOp);
55 TmpInst.addOperand(MCOp);
58 TmpInst.addOperand(MCOp);
67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 984 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); in EmitJump2Table()
985 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitJump2Table()
986 BrInst.addOperand(MCOperand::CreateReg(0)); in EmitJump2Table()
1031 Inst.addOperand(MCOperand::CreateReg(Dest)); in populateADROperands()
1032 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); in populateADROperands()
1034 Inst.addOperand(MCOperand::CreateImm(pred)); in populateADROperands()
1035 Inst.addOperand(MCOperand::CreateReg(ccreg)); in populateADROperands()
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); in EmitInstruction()
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); in EmitInstruction()
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
[all …]
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 577 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
583 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
622 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 620 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
626 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
636 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
688 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 230 ITInst.addOperand(MCOperand::createImm(ITState.Cond)); in flushPendingInstructions()
231 ITInst.addOperand(MCOperand::createImm(Mask)); in flushPendingInstructions()
1995 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
1997 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
1999 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
2014 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2016 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2021 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocNumOperands()
2026 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocRegOperands()
2031 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); in addCoprocOptionOperands()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 579 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
584 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
589 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
594 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
613 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
618 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
623 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
628 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
633 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
638 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
[all …]
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 1742 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
1744 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
1746 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1763 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1768 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocNumOperands()
1773 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocRegOperands()
1778 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); in addCoprocOptionOperands()
1783 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); in addITMaskOperands()
1788 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
[all …]
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 557 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
562 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
567 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
572 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
591 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
596 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
606 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
611 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
616 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); in addRegVSSRCOperands()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 538 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
539 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
540 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
546 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
547 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
548 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
558 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
559 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
564 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
565 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
[all …]
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 222 CompoundInsn->addOperand(Rt); in getCompoundInsn()
223 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
224 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
234 CompoundInsn->addOperand(Rt); in getCompoundInsn()
235 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
248 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 CompoundInsn->addOperand(Rt); in getCompoundInsn()
250 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
261 CompoundInsn->addOperand(Rs); in getCompoundInsn()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/ |
| D | MachineInstrTest.cpp | 121 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
122 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
125 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
126 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
141 MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
142 MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); in TEST()
145 MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
146 MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false)); in TEST()
194 VD1VU->addOperand(*MF, in TEST()
196 VD1VU->addOperand(*MF, in TEST()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 260 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset()
268 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
292 Inst.addOperand(Reg); in HexagonProcessInstruction()
293 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
294 Inst.addOperand(S16); in HexagonProcessInstruction()
301 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
308 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
315 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
322 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
329 Inst.addOperand(MCOperand::createExpr(C255)); in HexagonProcessInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 217 CompoundInsn->addOperand(Rt); in getCompoundInsn()
218 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
219 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
229 CompoundInsn->addOperand(Rt); in getCompoundInsn()
230 CompoundInsn->addOperand(Rs); in getCompoundInsn()
231 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
243 CompoundInsn->addOperand(Rs); in getCompoundInsn()
244 CompoundInsn->addOperand(Rt); in getCompoundInsn()
245 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
256 CompoundInsn->addOperand(Rs); in getCompoundInsn()
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 271 Inst.addOperand(Reg); in HexagonProcessInstruction()
272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
273 Inst.addOperand(S16); in HexagonProcessInstruction()
290 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
291 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
309 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
322 MappedInst.addOperand(Ps); in HexagonProcessInstruction()
385 TmpInst.addOperand(MappedInst.getOperand(0)); in HexagonProcessInstruction()
386 TmpInst.addOperand(MappedInst.getOperand(1)); in HexagonProcessInstruction()
[all …]
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 61 MI->addOperand(MachineOperand::CreateReg(RegNo,
76 MI->addOperand(MachineOperand::CreateImm(Val)); in addImm()
81 MI->addOperand(MachineOperand::CreateCImm(Val)); in addCImm()
86 MI->addOperand(MachineOperand::CreateFPImm(Val)); in addFPImm()
92 MI->addOperand(MachineOperand::CreateMBB(MBB, TargetFlags));
97 MI->addOperand(MachineOperand::CreateFI(Idx)); in addFrameIndex()
104 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
110 MI->addOperand(MachineOperand::CreateJTI(Idx, TargetFlags));
117 MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags));
123 MI->addOperand(MachineOperand::CreateES(FnName, TargetFlags));
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
62 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
63 Inst.addOperand(Op); in addOperand()
|
| /external/llvm/include/llvm/MC/ |
| D | MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
62 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
63 Inst.addOperand(Op); in addOperand()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 89 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
175 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
183 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
257 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
297 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
298 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
307 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
308 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
318 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
319 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
157 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
245 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
274 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
284 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
295 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 518 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
519 MOVI.addOperand(MCOperand::createImm(0)); in EmitFMov0()
527 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
528 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
532 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
533 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
537 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
538 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
573 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
574 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm())); in EmitInstruction()
[all …]
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 73 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
88 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
93 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
98 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
104 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
109 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
116 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
122 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
129 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
136 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 88 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
119 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
124 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
129 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
135 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
140 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
147 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
153 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
160 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
167 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 435 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
436 MOVI.addOperand(MCOperand::createImm(0)); in EmitFMov0()
444 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
445 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
449 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
450 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
494 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
503 TmpInst.addOperand(Dest); in EmitInstruction()
527 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
528 Adrp.addOperand(SymTLSDesc); in EmitInstruction()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); in tryAddingSymbolicOperand()
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); in tryAddingSymbolicOperand()
529 MI.addOperand(MCOperand::CreateExpr(Expr)); in tryAddingSymbolicOperand()
857 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPRRegisterClass()
901 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodetcGPRRegisterClass()
928 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeSPRRegisterClass()
949 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeDPRRegisterClass()
983 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeQPRRegisterClass()
993 Inst.addOperand(MCOperand::CreateImm(Val)); in DecodePredicateOperand()
995 Inst.addOperand(MCOperand::CreateReg(0)); in DecodePredicateOperand()
[all …]
|