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Searched refs:depth_mt (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen8_depth_state.c39 struct intel_mipmap_tree *depth_mt, in emit_depth_packets() argument
56 if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) { in emit_depth_packets()
71 (depth_mt ? depth_mt->surf.row_pitch - 1 : 0)); in emit_depth_packets()
72 if (depth_mt) { in emit_depth_packets()
73 OUT_RELOC64(depth_mt->bo, RELOC_WRITE, 0); in emit_depth_packets()
82 (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0)); in emit_depth_packets()
94 assert(depth_mt); in emit_depth_packets()
97 OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25); in emit_depth_packets()
98 OUT_RELOC64(depth_mt->hiz_buf->bo, RELOC_WRITE, 0); in emit_depth_packets()
99 OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2); in emit_depth_packets()
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Dgen6_depth_state.c39 struct intel_mipmap_tree *depth_mt, in gen6_emit_depth_stencil_hiz() argument
53 const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt; in gen6_emit_depth_stencil_hiz()
115 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | in gen6_emit_depth_stencil_hiz()
124 if (depth_mt) { in gen6_emit_depth_stencil_hiz()
125 OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0); in gen6_emit_depth_stencil_hiz()
160 assert(depth_mt); in gen6_emit_depth_stencil_hiz()
163 isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->surf, in gen6_emit_depth_stencil_hiz()
168 OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1); in gen6_emit_depth_stencil_hiz()
169 OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset); in gen6_emit_depth_stencil_hiz()
214 if (depth_mt) { in gen6_emit_depth_stencil_hiz()
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Dgen7_misc_state.c34 struct intel_mipmap_tree *depth_mt, in gen7_emit_depth_stencil_hiz() argument
51 const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt; in gen7_emit_depth_stencil_hiz()
109 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | in gen7_emit_depth_stencil_hiz()
117 if (depth_mt) { in gen7_emit_depth_stencil_hiz()
118 OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0); in gen7_emit_depth_stencil_hiz()
147 assert(depth_mt); in gen7_emit_depth_stencil_hiz()
152 (depth_mt->hiz_buf->pitch - 1)); in gen7_emit_depth_stencil_hiz()
153 OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, 0); in gen7_emit_depth_stencil_hiz()
178 if (depth_mt) { in gen7_emit_depth_stencil_hiz()
179 OUT_BATCH(brw_convert_depth_value(depth_mt->format, in gen7_emit_depth_stencil_hiz()
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Dbrw_misc_state.c206 struct intel_mipmap_tree *depth_mt = NULL; in brw_workaround_depthstencil_alignment() local
211 depth_mt = depth_irb->mt; in brw_workaround_depthstencil_alignment()
229 _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL) in brw_workaround_depthstencil_alignment()
239 stencil_irb->mt == depth_mt) { in brw_workaround_depthstencil_alignment()
266 struct intel_mipmap_tree *depth_mt = intel_renderbuffer_get_mt(depth_irb); in brw_emit_depthbuffer() local
289 depth_mt = stencil_mt; in brw_emit_depthbuffer()
292 if (depth_irb && depth_mt) { in brw_emit_depthbuffer()
302 assert(!_mesa_is_format_packed_depth_stencil(depth_mt->format)); in brw_emit_depthbuffer()
308 assert(devinfo->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0); in brw_emit_depthbuffer()
309 assert(!hiz || depth_mt->surf.tiling == ISL_TILING_Y0); in brw_emit_depthbuffer()
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Dintel_fbo.c643 struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL; in intel_validate_framebuffer() local
651 depth_mt = depthRb->mt; in intel_validate_framebuffer()
658 if (depth_mt && stencil_mt) { in intel_validate_framebuffer()
660 const unsigned d_width = depth_mt->surf.phys_level0_sa.width; in intel_validate_framebuffer()
661 const unsigned d_height = depth_mt->surf.phys_level0_sa.height; in intel_validate_framebuffer()
662 const unsigned d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ? in intel_validate_framebuffer()
663 depth_mt->surf.phys_level0_sa.depth : in intel_validate_framebuffer()
664 depth_mt->surf.phys_level0_sa.array_len; in intel_validate_framebuffer()
687 if (depth_mt == stencil_mt) { in intel_validate_framebuffer()
Dbrw_context.h735 struct intel_mipmap_tree *depth_mt,
1675 struct intel_mipmap_tree *depth_mt,
1685 struct intel_mipmap_tree *depth_mt,
1695 struct intel_mipmap_tree *depth_mt,
1704 struct intel_mipmap_tree *depth_mt,
Dbrw_blorp.c1392 struct intel_mipmap_tree *depth_mt = NULL; in brw_blorp_clear_depth_stencil() local
1395 depth_mt = find_miptree(GL_DEPTH_BUFFER_BIT, irb); in brw_blorp_clear_depth_stencil()
1401 intel_miptree_prepare_depth(brw, depth_mt, level, in brw_blorp_clear_depth_stencil()
1405 blorp_surf_for_miptree(brw, &depth_surf, depth_mt, depth_mt->aux_usage, in brw_blorp_clear_depth_stencil()
1452 intel_miptree_finish_depth(brw, depth_mt, level, in brw_blorp_clear_depth_stencil()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_fbo.c555 struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL; in intel_validate_framebuffer() local
563 depth_mt = depthRb->mt; in intel_validate_framebuffer()
567 if (depth_mt && stencil_mt) { in intel_validate_framebuffer()
572 if (depth_mt == stencil_mt) { in intel_validate_framebuffer()