Home
last modified time | relevance | path

Searched refs:dtpr2 (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/board/ti/ks2_evm/
Dddr3_k2g.c29 .dtpr2 = 0x50022A00ul,
69 .dtpr2 = 0x50023600ul,
130 .dtpr2 = 0x50022A00ul,
Dddr3_cfg.c27 .dtpr2 = 0x5002D200ul,
/external/u-boot/arch/arm/mach-keystone/
Dddr3_spd.c33 debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2); in dump_phy_config()
335 spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | in init_ddr3param()
338 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? in init_ddr3param()
342 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? in init_ddr3param()
Dddr3.c51 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); in ddr3_init_ddrphy()
/external/u-boot/arch/arm/mach-keystone/include/mach/
Dddr3.h27 unsigned int dtpr2; member
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dsdram.h84 u32 dtpr2; member
/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr.h136 u32 dtpr2; member
Dstm32mp1_ddr_regs.h156 u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/ member
Dstm32mp1_ddr.c145 DDRPHY_REG_TIMING(dtpr2),
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a23.h183 u32 dtpr2; /* 0x50 dram timing parameters register 2 */ member
Ddram_sun6i.h172 u32 dtpr2; /* 0x3c dram timing parameters register 2 */ member
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a23.c136 writel(dram_para.tpr4, &mctl_phy->dtpr2); in mctl_init()
Ddram_sun6i.c144 (MCTL_TEXSR << 0), &mctl_phy->dtpr2); in mctl_channel_init()
/external/u-boot/doc/device-tree-bindings/clock/
Drockchip,rk3288-dmc.txt91 dtpr2