Searched refs:getSpillAlignment (Results 1 – 19 of 19) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreMachineFunctionInfo.cpp | 47 TRI.getSpillAlignment(RC), true); in createLRSpillSlot()
61 TRI.getSpillAlignment(RC), true); in createFPSpillSlot()
74 unsigned Align = TRI.getSpillAlignment(RC); in createEHSpillSlot()
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| D | XCoreFrameLowering.cpp | 586 unsigned Align = TRI.getSpillAlignment(RC); in processFunctionBeforeFrameFinalized()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsMachineFunction.cpp | 64 TRI.getSpillAlignment(RC), false); in createEhDataRegsFI()
78 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); in createISRRegFI()
101 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false); in getMoveF64ViaSpillFI()
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| D | MipsSEFrameLowering.cpp | 896 TRI->getSpillAlignment(RC), in determineCalleeSaves()
913 TRI->getSpillAlignment(RC), in determineCalleeSaves()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVExtract.cpp | 127 HRI.getSpillAlignment(VecRC)); in runOnMachineFunction()
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| D | HexagonFrameLowering.cpp | 1501 unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment()); in assignCalleeSavedSpillSlots()
1725 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec2()
1772 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec2()
1811 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec()
1839 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec()
1935 unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC); in determineCalleeSaves()
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| D | HexagonInstrInfo.cpp | 882 unsigned RegAlign = TRI->getSpillAlignment(*RC); in storeRegToStackSlot()
948 unsigned RegAlign = TRI->getSpillAlignment(*RC); in loadRegFromStackSlot()
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| D | HexagonISelLowering.cpp | 437 unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in LowerCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 260 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 326 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 97 unsigned Align = TRI->getSpillAlignment(*RC); in createSpillSlot()
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| D | RegisterScavenging.cpp | 469 unsigned NeedAlign = TRI->getSpillAlignment(RC); in spill()
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| D | RegAllocFast.cpp | 241 unsigned Align = TRI->getSpillAlignment(RC); in getStackSpaceFor()
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| D | PrologEpilogInserter.cpp | 379 unsigned Align = RegInfo->getSpillAlignment(*RC); in assignCalleeSavedSpillSlots()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCFrameLowering.cpp | 423 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1509 unsigned Align = TRI->getSpillAlignment(RC); in determineCalleeSaves()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1936 unsigned Align = TRI.getSpillAlignment(RC); in addScavengingSpillSlot()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 2015 unsigned Align = TRI->getSpillAlignment(RC); in determineCalleeSaves()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 2000 unsigned Align = TRI->getSpillAlignment(*RC); in assignCalleeSavedSpillSlots()
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