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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dtls-relocs.s7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:var
219 movn x4, #:tprel_g2:var
231 movn x6, #:tprel_g1:var
233 movn w8, #:tprel_g1:var
263 movn x12, #:tprel_g0:var
[all …]
Darm64-aliases.s166 movn x0, #0
167 movn x0, #0, lsl #16
168 movn x0, #0, lsl #32
169 movn x0, #0, lsl #48
170 movn w0, #0
171 movn w0, #0, lsl #16
173 ; CHECK: movn x0, #0x0, lsl #16
174 ; CHECK: movn x0, #0x0, lsl #32
175 ; CHECK: movn x0, #0x0, lsl #48
177 ; CHECK: movn w0, #0x0, lsl #16
[all …]
Darm64-tls-relocs.s43 movn x4, #:tprel_g2:var
54 movn x6, #:tprel_g1:var
80 movn x12, #:tprel_g0:var
176 movn x4, #:dtprel_g2:var
187 movn x6, #:dtprel_g1:var
213 movn x12, #:dtprel_g0:var
Delf-reloc-movw.s17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
/external/llvm/test/MC/AArch64/
Dtls-relocs.s7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:var
219 movn x4, #:tprel_g2:var
231 movn x6, #:tprel_g1:var
233 movn w8, #:tprel_g1:var
263 movn x12, #:tprel_g0:var
[all …]
Darm64-aliases.s166 movn x0, #0
167 movn x0, #0, lsl #16
168 movn x0, #0, lsl #32
169 movn x0, #0, lsl #48
170 movn w0, #0
171 movn w0, #0, lsl #16
173 ; CHECK: movn x0, #0x0, lsl #16
174 ; CHECK: movn x0, #0x0, lsl #32
175 ; CHECK: movn x0, #0x0, lsl #48
177 ; CHECK: movn w0, #0x0, lsl #16
[all …]
Darm64-tls-relocs.s44 movn x4, #:tprel_g2:var
55 movn x6, #:tprel_g1:var
81 movn x12, #:tprel_g0:var
168 movn x4, #:dtprel_g2:var
179 movn x6, #:dtprel_g1:var
205 movn x12, #:dtprel_g0:var
Delf-reloc-movw.s17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-select.ll57 ; MIPS32: movn [[T1]],[[T2]],[[T3]]
72 ; MIPS32: movn [[T2]],[[T3]],[[T14]]
89 ; MIPS32: movn [[T1]],[[T3]],[[T14]]
100 ; MIPS32: movn [[T10]],[[T6]],[[T16]]
112 ; MIPS32: movn [[T14]],[[T16]],[[T6]]
127 ; MIPS32: movn [[T15]],[[T16]],[[T6]]
144 ; MIPS32: movn [[T14]],[[T16]],[[T6]]
155 ; MIPS32: movn [[T11]],[[T7]],[[T17]]
167 ; MIPS32: movn [[T16]],[[T7]],[[T6]]
182 ; MIPS32: movn [[T17]],[[T7]],[[T6]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dashr.ll308 ; MIPS32-NEXT: movn $3, $2, $1
311 ; MIPS32-NEXT: movn $2, $4, $1
322 ; 32R2-NEXT: movn $3, $2, $1
325 ; 32R2-NEXT: movn $2, $4, $1
374 ; MMR3-NEXT: movn $3, $2, $5
377 ; MMR3-NEXT: movn $2, $1, $5
546 ; MIPS32-NEXT: movn $8, $zero, $12
547 ; MIPS32-NEXT: movn $1, $10, $13
557 ; MIPS32-NEXT: movn $1, $8, $14
563 ; MIPS32-NEXT: movn $1, $gp, $25
[all …]
Dlshr.ll333 ; MIPS32-NEXT: movn $3, $2, $1
335 ; MIPS32-NEXT: movn $2, $zero, $1
346 ; MIPS32R2-NEXT: movn $3, $2, $1
348 ; MIPS32R2-NEXT: movn $2, $zero, $1
399 ; MMR3-NEXT: movn $3, $2, $4
402 ; MMR3-NEXT: movn $2, $5, $4
560 ; MIPS32-NEXT: movn $1, $zero, $11
568 ; MIPS32-NEXT: movn $3, $13, $14
578 ; MIPS32-NEXT: movn $1, $8, $15
580 ; MIPS32-NEXT: movn $1, $3, $25
[all …]
Dshl.ll365 ; MIPS32-NEXT: movn $2, $3, $1
367 ; MIPS32-NEXT: movn $3, $zero, $1
378 ; MIPS32R2-NEXT: movn $2, $3, $1
380 ; MIPS32R2-NEXT: movn $3, $zero, $1
431 ; MMR3-NEXT: movn $2, $3, $4
434 ; MMR3-NEXT: movn $3, $5, $4
594 ; MIPS32-NEXT: movn $2, $zero, $10
602 ; MIPS32-NEXT: movn $3, $12, $13
612 ; MIPS32-NEXT: movn $2, $3, $14
614 ; MIPS32-NEXT: movn $2, $15, $25
[all …]
Dselect-int.ll47 ; CMOV: movn $6, $5, $[[T0]]
56 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
83 ; CMOV: movn $6, $5, $[[T0]]
92 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
119 ; CMOV: movn $6, $5, $[[T0]]
129 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
162 ; CMOV-32: movn $2, $6, $[[T0]]
164 ; CMOV-32: movn $3, $7, $[[T0]]
185 ; CMOV-64: movn $6, $5, $[[T0]]
197 ; MM32R3: movn $2, $6, $[[T0]] # <MCInst #{{[0-9]+}} MOVN_I_MM
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-int.ll46 ; CMOV: movn $6, $5, $[[T0]]
55 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
81 ; CMOV: movn $6, $5, $[[T0]]
90 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
116 ; CMOV: movn $6, $5, $[[T0]]
125 ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
158 ; CMOV-32: movn $2, $6, $[[T0]]
160 ; CMOV-32: movn $3, $7, $[[T0]]
181 ; CMOV-64: movn $6, $5, $[[T0]]
193 ; MM32R3: movn $2, $6, $[[T0]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll11 ; CHECK-NEXT: movn $6, $5, $1
29 ; CHECK-NEXT: movn $6, $5, $1
47 ; CHECK-NEXT: movn $6, $5, $1
63 ; CHECK-NEXT: movn $6, $5, $1
81 ; CHECK-NEXT: movn.s $f0, $f1, $1
96 ; CHECK-NEXT: movn.s $f0, $f12, $1
113 ; CHECK-NEXT: movn.d $f0, $f2, $1
129 ; CHECK-NEXT: movn.d $f0, $f12, $1
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll12 ; CHECK-NEXT: movn $6, $5, $[[T2]]
29 ; CHECK-NEXT: movn $6, $5, $[[T4]]
46 ; CHECK-NEXT: movn $6, $5, $[[T4]]
61 ; CHECK-NEXT: movn $6, $5, $[[T2]]
77 ; CHECK: movn.s $f0, $f1, $[[T2]]
93 ; CHECK: movn.d $f0, $f2, $[[T2]]
/external/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s13 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
20 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
24 movn $9, $6, $7
/external/llvm/test/CodeGen/Mips/
Dcmov.ll16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
28 ; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4
56 ; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $4
68 ; 64-CMOV: movn $[[R1]], $[[R0]], $4
128 ; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]
138 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
200 ; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]
201 ; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]
216 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
279 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
[all …]
Dzeroreg.ll16 ; 32-CMOV: movn $2, $zero, $4
22 ; 64-CMOV: movn $2, $zero, $4
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4
73 ; 64-CMOV: movn $2, $zero, $4
Dselect.ll15 ; 32: movn $5, $6, $4
18 ; 32R2: movn $5, $6, $4
25 ; 64: movn $5, $6, $4
28 ; 64R2: movn $5, $6, $4
45 ; 32-DAG: movn $6, $[[F1]], $4
47 ; 32: movn $7, $[[F1H]], $4
52 ; 32R2-DAG: movn $6, $[[F1]], $4
54 ; 32R2: movn $7, $[[F1H]], $4
67 ; 64: movn $5, $6, $4
70 ; 64R2: movn $5, $6, $4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dcmov.ll16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
28 ; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4
56 ; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $4
68 ; 64-CMOV: movn $[[R1]], $[[R0]], $4
128 ; 32-CMOV: movn ${{[26]}}, $5, $[[R1]]
138 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
200 ; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]]
201 ; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]]
216 ; 64-CMOV: movn ${{[26]}}, $5, $[[R1]]
279 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
[all …]
Dzeroreg.ll16 ; 32-CMOV: movn $2, $zero, $4
22 ; 64-CMOV: movn $2, $zero, $4
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4
73 ; 64-CMOV: movn $2, $zero, $4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmicromips-movcond-instructions.s14 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
25 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
32 movn $9, $6, $7
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class3_chroma.s137 movn x20,#0
146 movn x20,#0
173 movn x20,#0
182 movn x20,#0
222 movn x20,#0
231 movn x20,#0
260 movn x20,#0
269 movn x20,#0
423 movn x20,#0
431 movn x20,#0
[all …]
Dihevc_sao_edge_offset_class2_chroma.s142 movn x20,#0
150 movn x20,#0
181 movn x20,#0
188 movn x20,#0
230 movn x20,#0
240 movn x20,#0
269 movn x20,#0
279 movn x20,#0
439 movn x20,#0
446 movn x20,#0
[all …]

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