Searched refs:mpuclk (Results 1 – 8 of 8) sorted by relevance
27 u32 mpuclk; member135 { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },296 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) in cm_calc_handoff_mpu_clk_hz()301 clk_hz /= ((main_cfg->mpuclk >> in cm_calc_handoff_mpu_clk_hz()434 clk = main_cfg->mpuclk; in cm_calculate_numer()446 clk = main_cfg->mpuclk; in cm_calculate_numer()735 writel(main_cfg->mpuclk, in cm_full_cfg()796 &clock_manager_base->main_pll.mpuclk); in cm_full_cfg()974 mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz()979 reg = readl(&clock_manager_base->altera.mpuclk); in cm_get_mpu_clk_hz()
147 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()150 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); in cm_basic_init()365 reg = readl(&clock_manager_base->altera.mpuclk); in cm_get_mpu_clk_hz()367 reg = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz()
118 writel(0xff, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()137 writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()237 unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz()267 clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) & in cm_get_mpu_clk_hz()
14 u32 mpuclk; member51 u32 mpuclk; member95 u32 mpuclk; member
20 u32 mpuclk; member65 u32 mpuclk; member
79 u32 mpuclk; member
76 mpuclk-cnt = <0>; /* Field: mpuclk.cnt */77 mpuclk-src = <0>; /* Field: mpuclk.src */129 mpuclk = <0x03840001>; /* Register: mpuclk */
142 mpuclk: mpuclk { label279 clocks = <&mpuclk>;286 clocks = <&mpuclk>;