| /external/u-boot/arch/arm/dts/ |
| D | zynq-7000.dtsi | 85 clock-names = "can_clk", "pclk";
97 clock-names = "can_clk", "pclk";
166 clock-names = "uart_clk", "pclk";
175 clock-names = "uart_clk", "pclk";
187 clock-names = "ref_clk", "pclk";
199 clock-names = "ref_clk", "pclk";
205 clock-names = "ref_clk", "pclk";
222 clock-names = "pclk", "hclk", "tx_clk";
233 clock-names = "pclk", "hclk", "tx_clk";
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| D | zynqmp-clk-ccf.dtsi | 193 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
198 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
203 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
208 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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| D | zynqmp.dtsi | 242 clock-names = "can_clk", "pclk";
253 clock-names = "can_clk", "pclk";
513 clock-names = "pclk", "hclk", "tx_clk";
526 clock-names = "pclk", "hclk", "tx_clk";
539 clock-names = "pclk", "hclk", "tx_clk";
552 clock-names = "pclk", "hclk", "tx_clk";
638 clock-names = "ref_clk", "pclk";
759 clock-names = "ref_clk", "pclk";
770 clock-names = "ref_clk", "pclk";
818 clock-names = "uart_clk", "pclk";
[all …]
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| D | meson-gxbb.dtsi | 748 clock-names = "xtal", "pclk", "baud";
753 clock-names = "xtal", "pclk", "baud";
758 clock-names = "xtal", "pclk", "baud";
763 clock-names = "xtal", "pclk", "baud";
768 clock-names = "xtal", "pclk", "baud";
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| D | meson-gxl.dtsi | 757 clock-names = "xtal", "pclk", "baud";
762 clock-names = "xtal", "pclk", "baud";
767 clock-names = "xtal", "pclk", "baud";
772 clock-names = "xtal", "pclk", "baud";
777 clock-names = "xtal", "pclk", "baud";
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| D | rk3399.dtsi | 215 "pm", "pclk", "aclk";
443 clock-names = "i2c", "pclk";
458 clock-names = "i2c", "pclk";
473 clock-names = "i2c", "pclk";
488 clock-names = "i2c", "pclk";
503 clock-names = "i2c", "pclk";
518 clock-names = "i2c", "pclk";
1065 clock-names = "i2c", "pclk";
1080 clock-names = "i2c", "pclk";
1331 clock-names = "pclk", "timer";
[all …]
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| D | zynqmp-r5.dts | 69 clock-names = "uart_clk", "pclk";
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| D | at91sam9x5_macb1.dtsi | 50 clock-names = "hclk", "pclk";
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| D | sama5d3_emac.dtsi | 50 clock-names = "hclk", "pclk";
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| D | at91sam9261.dtsi | 134 clock-names = "pclk", "hclk";
210 clock-names = "pclk";
221 clock-names = "pclk";
232 clock-names = "pclk";
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| D | at91sam9x5_macb0.dtsi | 62 clock-names = "hclk", "pclk";
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| D | zynq-cse-qspi.dtsi | 52 clock-names = "ref_clk", "pclk";
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| D | at91sam9263.dtsi | 844 clock-names = "pclk";
855 clock-names = "pclk";
877 clock-names = "hclk", "pclk";
886 clock-names = "pclk", "hclk";
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| D | sama5d3_gmac.dtsi | 83 clock-names = "hclk", "pclk";
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| D | stm32429i-eval.dts | 143 pclk-sample = <1>;
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| /external/u-boot/arch/arm/mach-exynos/ |
| D | clock.c | 639 unsigned long pclk, sclk; in exynos4_get_pwm_clk() local
672 pclk = sclk / (ratio + 1); in exynos4_get_pwm_clk()
674 return pclk; in exynos4_get_pwm_clk()
680 unsigned long pclk, sclk; in exynos4x12_get_pwm_clk() local
686 pclk = sclk / (ratio + 1); in exynos4x12_get_pwm_clk()
688 return pclk; in exynos4x12_get_pwm_clk()
916 unsigned long pclk, sclk; in exynos4_get_lcd_clk() local
948 pclk = sclk / (ratio + 1); in exynos4_get_lcd_clk()
950 return pclk; in exynos4_get_lcd_clk()
958 unsigned long pclk, sclk; in exynos5_get_lcd_clk() local
[all …]
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| /external/perfetto/src/traced/probes/ftrace/test/data/android_flounder_lte_LRX16F_3.10.40/events/display/display_mode/ |
| D | format | 11 field:unsigned long pclk; offset:16; size:8; signed:0;
24 …h: H=%d V=%d back_porch: H=%d V=%d active: H=%d V=%d front_porch: H=%d V=%d pclk=%ld stereo mode=%d
25 …, REC->h_active, REC->v_active, REC->h_front_porch, REC->v_front_porch, REC->pclk, REC->stereo_mode
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| /external/u-boot/doc/device-tree-bindings/spi/ |
| D | spi-zynq-qspi.txt | 10 - clock-names : List of input clock names - "ref_clk", "pclk"
20 clock-names = "ref_clk", "pclk";
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| D | spi-zynq.txt | 10 - clock-names : List of input clock names - "ref_clk", "pclk"
25 clock-names = "ref_clk", "pclk";
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| /external/u-boot/arch/arm/mach-s5pc1xx/ |
| D | clock.c | 246 unsigned long pclk; in get_pclk_sys() local
262 pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1); in get_pclk_sys()
264 return pclk; in get_pclk_sys()
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| /external/u-boot/drivers/video/stm32/ |
| D | stm32_ltdc.c | 334 struct clk pclk; in stm32_ltdc_probe() local
344 ret = clk_get_by_index(dev, 0, &pclk); in stm32_ltdc_probe()
350 ret = clk_enable(&pclk); in stm32_ltdc_probe()
388 rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ); in stm32_ltdc_probe()
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| /external/u-boot/drivers/net/pfe_eth/ |
| D | pfe_mdio.c | 253 u32 pclk = 250000000; in pfe_mdio_init() local
268 mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT); in pfe_mdio_init()
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| /external/u-boot/drivers/video/tegra124/ |
| D | display.c | 28 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh() local
34 if (!pclk || !h_total || !v_total) in tegra_dc_calc_refresh()
36 refresh = pclk / h_total; in tegra_dc_calc_refresh()
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | nvidia,tegra20-car.txt | 141 110 pclk
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| /external/u-boot/drivers/net/ |
| D | fec_mxc.c | 140 u32 pclk = imx_get_fecclk(); in fec_mii_setspeed() local
141 u32 speed = DIV_ROUND_UP(pclk, 5000000); in fec_mii_setspeed()
142 u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; in fec_mii_setspeed()
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