Home
last modified time | relevance | path

Searched refs:per_pll (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_s10.c32 writel(val, &clock_manager_base->per_pll.bypass); in cm_write_bypass_perpll()
93 &clock_manager_base->per_pll.pllglob); in cm_basic_init()
94 writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck); in cm_basic_init()
95 writel(vcocalib, &clock_manager_base->per_pll.vcocalib); in cm_basic_init()
96 writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); in cm_basic_init()
97 writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); in cm_basic_init()
98 writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl); in cm_basic_init()
99 writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv); in cm_basic_init()
104 setbits_le32(&clock_manager_base->per_pll.pllglob, in cm_basic_init()
128 writel(0xff, &clock_manager_base->per_pll.cntr2clk); in cm_basic_init()
[all …]
Dclock_manager_gen5.c82 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
83 &clock_manager_base->per_pll.en); in cm_basic_init()
97 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
109 &clock_manager_base->per_pll.vco); in cm_basic_init()
122 &clock_manager_base->per_pll.src); in cm_basic_init()
128 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
137 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
163 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); in cm_basic_init()
166 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); in cm_basic_init()
171 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); in cm_basic_init()
[all …]
Dclock_manager_arria10.c573 &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
578 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
633 writel(0, &clock_manager_base->per_pll.en); in cm_full_cfg()
639 &clock_manager_base->per_pll.bypasss); in cm_full_cfg()
654 &clock_manager_base->per_pll.vco0); in cm_full_cfg()
657 writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); in cm_full_cfg()
702 &clock_manager_base->per_pll.vco1); in cm_full_cfg()
706 &clock_manager_base->per_pll.vco1); in cm_full_cfg()
715 clrbits_le32(&clock_manager_base->per_pll.vco0, in cm_full_cfg()
727 writel((readl(&clock_manager_base->per_pll.vco0) & in cm_full_cfg()
[all …]
/external/u-boot/drivers/mmc/
Dsocfpga_dw_mmc.c43 clrbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
54 setbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_s10.h139 struct socfpga_clock_manager_per_pll per_pll; member
Dclock_manager_arria10.h88 struct socfpga_clock_manager_per_pll per_pll; member
Dclock_manager_gen5.h108 struct socfpga_clock_manager_per_pll per_pll; member