Searched refs:pipelined (Results 1 – 25 of 59) sorted by relevance
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6 ; which enables the loop to be pipelined. In this test, the loop should7 ; not be pipelined when the chained references are constrained correctly.9 ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
5 ; Check if the first loop is pipelined.12 ; Check if the second loop is pipelined.
3 ; Test that we fixup a pipelined loop correctly when the number of
6 ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
9 ; STATS: 1 pipeliner - Number of loops software pipelined
6 ; STATS: 1 pipeliner - Number of loops software pipelined
3 ; Check that the pipelined code uses the proper address in the
4 ; STATS: 1 pipeliner - Number of loops software pipelined
8 ; Test that we change the CFG correctly for pipelined loops where the trip
4 ; function. The pipelined code should have two packets.
6 ; Phi. When the loop is pipelined, the Phi that generates the operand value
3 ; Very similar to swp-stages4.ll, but the pipelined schedule is a little
10 ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
4 ; Phis that do not occur in the loop that is being pipelined.
3 ; Test that the pipeliner correctly fixes up the pipelined CFG when the loop
412 const bool pipelined) in store_query_result_reg() argument422 (pipelined ? MI_STORE_REGISTER_MEM_PREDICATE : 0) | in store_query_result_reg()442 const bool pipelined = brw_is_query_pipelined(query); in hsw_store_query_result() local448 } else if (pname == GL_QUERY_RESULT_AVAILABLE && !pipelined) { in hsw_store_query_result()458 if (pipelined) in hsw_store_query_result()461 pipelined); in hsw_store_query_result()
64 // pipelined with that of the TensorCore. This parameter only affects results68 // false: The execution of the sparse core is not pipelined with that of the76 // true: The execution of the sparse core is pipelined with that of the
5 ; function. The pipelined code should have two packets.
17 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
15 // The Cortex-R52 is an in-order pipelined superscalar microprocessor with17 // There are two ALUs, one LDST, one MUL and a non-pipelined integer DIV.76 let Latency = 8; let ResourceCycles = [8]; // non-pipelined111 let ResourceCycles = [7]; // is not pipelined149 let Latency = 8; let ResourceCycles = [8]; // not pipelined
8 ; CHECK: Number of loops software pipelined
9 ; should be nicely pipelined.
40 // Instruction stage - These values represent a non-pipelined step in