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Searched refs:radeon_emit (Results 1 – 25 of 44) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_msaa.c153 radeon_emit(cs, sample_locs_8x[0]); in si_emit_sample_locations()
154 radeon_emit(cs, sample_locs_8x[4]); in si_emit_sample_locations()
155 radeon_emit(cs, 0); in si_emit_sample_locations()
156 radeon_emit(cs, 0); in si_emit_sample_locations()
157 radeon_emit(cs, sample_locs_8x[1]); in si_emit_sample_locations()
158 radeon_emit(cs, sample_locs_8x[5]); in si_emit_sample_locations()
159 radeon_emit(cs, 0); in si_emit_sample_locations()
160 radeon_emit(cs, 0); in si_emit_sample_locations()
161 radeon_emit(cs, sample_locs_8x[2]); in si_emit_sample_locations()
162 radeon_emit(cs, sample_locs_8x[6]); in si_emit_sample_locations()
[all …]
Dcik_sdma.c54 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY, in cik_sdma_copy_buffer()
57 radeon_emit(cs, ctx->b.chip_class >= GFX9 ? csize - 1 : csize); in cik_sdma_copy_buffer()
58 radeon_emit(cs, 0); /* src/dst endian swap */ in cik_sdma_copy_buffer()
59 radeon_emit(cs, src_offset); in cik_sdma_copy_buffer()
60 radeon_emit(cs, src_offset >> 32); in cik_sdma_copy_buffer()
61 radeon_emit(cs, dst_offset); in cik_sdma_copy_buffer()
62 radeon_emit(cs, dst_offset >> 32); in cik_sdma_copy_buffer()
99 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_PACKET_CONSTANT_FILL, 0, in cik_sdma_clear_buffer()
101 radeon_emit(cs, offset); in cik_sdma_clear_buffer()
102 radeon_emit(cs, offset >> 32); in cik_sdma_clear_buffer()
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Dsi_state_draw.c269 radeon_emit(cs, offchip_layout); in si_emit_derived_tess_state()
270 radeon_emit(cs, tcs_out_offsets); in si_emit_derived_tess_state()
271 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); in si_emit_derived_tess_state()
283 radeon_emit(cs, ls_current->config.rsrc1); in si_emit_derived_tess_state()
284 radeon_emit(cs, ls_rsrc2); in si_emit_derived_tess_state()
289 radeon_emit(cs, offchip_layout); in si_emit_derived_tess_state()
290 radeon_emit(cs, tcs_out_offsets); in si_emit_derived_tess_state()
291 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); in si_emit_derived_tess_state()
292 radeon_emit(cs, tcs_in_layout); in si_emit_derived_tess_state()
297 radeon_emit(cs, offchip_layout); in si_emit_derived_tess_state()
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Dsi_state_streamout.c246 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_vgt_streamout()
247 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); in si_flush_vgt_streamout()
249 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_flush_vgt_streamout()
250 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ in si_flush_vgt_streamout()
251 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ in si_flush_vgt_streamout()
252 radeon_emit(cs, 0); in si_flush_vgt_streamout()
253 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */ in si_flush_vgt_streamout()
254 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */ in si_flush_vgt_streamout()
255 radeon_emit(cs, 4); /* poll interval */ in si_flush_vgt_streamout()
278 radeon_emit(cs, (t[i]->b.buffer_offset + in si_emit_streamout_begin()
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Dsi_perfcounter.c482 radeon_emit(cs, shaders & 0x7f); in si_pc_emit_shaders()
483 radeon_emit(cs, 0xffffffff); in si_pc_emit_shaders()
510 radeon_emit(cs, 0); in si_pc_emit_select()
512 radeon_emit(cs, selectors[idx] | regs->select_or); in si_pc_emit_select()
521 radeon_emit(cs, 0); in si_pc_emit_select()
525 radeon_emit(cs, selectors[idx] | regs->select_or); in si_pc_emit_select()
534 radeon_emit(cs, 0); in si_pc_emit_select()
536 radeon_emit(cs, selectors[idx] | regs->select_or); in si_pc_emit_select()
542 radeon_emit(cs, 0); in si_pc_emit_select()
561 radeon_emit(cs, 0); in si_pc_emit_select()
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Dsi_compute.c284 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_initialize_compute()
285 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff)); in si_initialize_compute()
291 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) | in si_initialize_compute()
293 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) | in si_initialize_compute()
315 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */ in si_initialize_compute()
316 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */ in si_initialize_compute()
452 radeon_emit(cs, shader_va >> 8); in si_switch_compute_shader()
453 radeon_emit(cs, shader_va >> 40); in si_switch_compute_shader()
456 radeon_emit(cs, config->rsrc1); in si_switch_compute_shader()
457 radeon_emit(cs, config->rsrc2); in si_switch_compute_shader()
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Dsi_dma.c66 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, in si_dma_copy_buffer()
68 radeon_emit(cs, dst_offset); in si_dma_copy_buffer()
69 radeon_emit(cs, src_offset); in si_dma_copy_buffer()
70 radeon_emit(cs, (dst_offset >> 32UL) & 0xff); in si_dma_copy_buffer()
71 radeon_emit(cs, (src_offset >> 32UL) & 0xff); in si_dma_copy_buffer()
108 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_CONSTANT_FILL, 0, in si_dma_clear_buffer()
110 radeon_emit(cs, offset); in si_dma_clear_buffer()
111 radeon_emit(cs, clear_value); in si_dma_clear_buffer()
112 radeon_emit(cs, (offset >> 32) << 16); in si_dma_clear_buffer()
201 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd, size / 4)); in si_dma_copy_tile()
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Dsi_state_viewport.c130 radeon_emit(cs, S_028250_TL_X(final.minx) | in si_emit_one_scissor()
133 radeon_emit(cs, S_028254_BR_X(final.maxx) | in si_emit_one_scissor()
208 radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */ in si_emit_guardband()
209 radeon_emit(cs, fui(discard_y)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */ in si_emit_guardband()
210 radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */ in si_emit_guardband()
211 radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */ in si_emit_guardband()
293 radeon_emit(cs, fui(state->scale[0])); in si_emit_one_viewport()
294 radeon_emit(cs, fui(state->translate[0])); in si_emit_one_viewport()
295 radeon_emit(cs, fui(state->scale[1])); in si_emit_one_viewport()
296 radeon_emit(cs, fui(state->translate[1])); in si_emit_one_viewport()
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Dsi_cp_dma.c102 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); in si_emit_cp_dma()
103 radeon_emit(cs, header); in si_emit_cp_dma()
104 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
105 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */ in si_emit_cp_dma()
106 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */ in si_emit_cp_dma()
107 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */ in si_emit_cp_dma()
108 radeon_emit(cs, command); in si_emit_cp_dma()
112 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in si_emit_cp_dma()
113 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
114 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */ in si_emit_cp_dma()
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Dsi_state.c119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_cb_render_state()
120 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0)); in si_emit_cb_render_state()
266 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */ in si_emit_cb_render_state()
267 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */ in si_emit_cb_render_state()
268 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */ in si_emit_cb_render_state()
271 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */ in si_emit_cb_render_state()
272 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */ in si_emit_cb_render_state()
273 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */ in si_emit_cb_render_state()
1088 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) | in si_emit_stencil_ref()
1092 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | in si_emit_stencil_ref()
[all …]
/external/mesa3d/src/gallium/drivers/r600/
Dcayman_msaa.c168 radeon_emit(cs, cm_sample_locs_8x[0]); in cayman_emit_msaa_sample_locs()
169 radeon_emit(cs, cm_sample_locs_8x[4]); in cayman_emit_msaa_sample_locs()
170 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
171 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
172 radeon_emit(cs, cm_sample_locs_8x[1]); in cayman_emit_msaa_sample_locs()
173 radeon_emit(cs, cm_sample_locs_8x[5]); in cayman_emit_msaa_sample_locs()
174 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
175 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
176 radeon_emit(cs, cm_sample_locs_8x[2]); in cayman_emit_msaa_sample_locs()
177 radeon_emit(cs, cm_sample_locs_8x[6]); in cayman_emit_msaa_sample_locs()
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Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_vgt_streamout()
170 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); in r600_flush_vgt_streamout()
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in r600_flush_vgt_streamout()
173 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ in r600_flush_vgt_streamout()
174 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ in r600_flush_vgt_streamout()
175 radeon_emit(cs, 0); in r600_flush_vgt_streamout()
176 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */ in r600_flush_vgt_streamout()
177 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */ in r600_flush_vgt_streamout()
178 radeon_emit(cs, 4); /* poll interval */ in r600_flush_vgt_streamout()
201 radeon_emit(cs, (t[i]->b.buffer_offset + in r600_emit_streamout_begin()
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Dr600_hw_context.c122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
123 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in r600_flush_emit()
136 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
137 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in r600_flush_emit()
142 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
143 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in r600_flush_emit()
156 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
157 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_flush_emit()
230 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); in r600_flush_emit()
231 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ in r600_flush_emit()
[all …]
Dr600_cs.h126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
127 radeon_emit(cs, reloc); in r600_emit_reloc()
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
136 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
142 radeon_emit(cs, value); in radeon_set_config_reg()
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
150 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
156 radeon_emit(cs, value); in radeon_set_context_reg()
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
166 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
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Devergreen_hw_context.c71 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize)); in evergreen_dma_copy_buffer()
72 radeon_emit(cs, dst_offset & 0xffffffff); in evergreen_dma_copy_buffer()
73 radeon_emit(cs, src_offset & 0xffffffff); in evergreen_dma_copy_buffer()
74 radeon_emit(cs, (dst_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
75 radeon_emit(cs, (src_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
131 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in evergreen_cp_dma_clear_buffer()
132 radeon_emit(cs, clear_value); /* DATA [31:0] */ in evergreen_cp_dma_clear_buffer()
133 radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */ in evergreen_cp_dma_clear_buffer()
134 radeon_emit(cs, offset); /* DST_ADDR_LO [31:0] */ in evergreen_cp_dma_clear_buffer()
135 radeon_emit(cs, (offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */ in evergreen_cp_dma_clear_buffer()
[all …]
Devergreen_state.c971 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs)); in evergreen_emit_config_state()
972 radeon_emit(cs, 0); in evergreen_emit_config_state()
973 radeon_emit(cs, 0); in evergreen_emit_config_state()
975 radeon_emit(cs, a->sq_gpr_resource_mgmt_1); in evergreen_emit_config_state()
976 radeon_emit(cs, a->sq_gpr_resource_mgmt_2); in evergreen_emit_config_state()
977 radeon_emit(cs, a->sq_gpr_resource_mgmt_3); in evergreen_emit_config_state()
1671 radeon_emit(cs, S_028C00_LAST_PIXEL(1) | in evergreen_emit_msaa_state()
1673 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | in evergreen_emit_msaa_state()
1681 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ in evergreen_emit_msaa_state()
1682 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ in evergreen_emit_msaa_state()
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Dr600_state.c275 radeon_emit(cs, fui(offset_scale)); in r600_emit_polygon_offset()
276 radeon_emit(cs, fui(offset_units)); in r600_emit_polygon_offset()
277 radeon_emit(cs, fui(offset_scale)); in r600_emit_polygon_offset()
278 radeon_emit(cs, fui(offset_units)); in r600_emit_polygon_offset()
1299 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */ in r600_emit_msaa_state()
1300 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */ in r600_emit_msaa_state()
1308 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ in r600_emit_msaa_state()
1309 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ in r600_emit_msaa_state()
1314 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ in r600_emit_msaa_state()
1315 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ in r600_emit_msaa_state()
[all …]
Devergreen_compute.c610 radeon_emit(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */ in evergreen_emit_dispatch()
611 radeon_emit(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */ in evergreen_emit_dispatch()
612 radeon_emit(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */ in evergreen_emit_dispatch()
618 radeon_emit(cs, info->block[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */ in evergreen_emit_dispatch()
619 radeon_emit(cs, info->block[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */ in evergreen_emit_dispatch()
620 radeon_emit(cs, info->block[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */ in evergreen_emit_dispatch()
634 radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0)); in evergreen_emit_dispatch()
635 radeon_emit(cs, info->grid[0]); in evergreen_emit_dispatch()
636 radeon_emit(cs, info->grid[1]); in evergreen_emit_dispatch()
637 radeon_emit(cs, info->grid[2]); in evergreen_emit_dispatch()
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Dr600_viewport.c175 radeon_emit(cs, S_028250_TL_X(final.minx) | in r600_emit_one_scissor()
178 radeon_emit(cs, S_028254_BR_X(final.maxx) | in r600_emit_one_scissor()
230 radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */ in r600_emit_guardband()
231 radeon_emit(cs, fui(1.0)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */ in r600_emit_guardband()
232 radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */ in r600_emit_guardband()
233 radeon_emit(cs, fui(1.0)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */ in r600_emit_guardband()
311 radeon_emit(cs, fui(state->scale[0])); in r600_emit_one_viewport()
312 radeon_emit(cs, fui(state->translate[0])); in r600_emit_one_viewport()
313 radeon_emit(cs, fui(state->scale[1])); in r600_emit_one_viewport()
314 radeon_emit(cs, fui(state->translate[1])); in r600_emit_one_viewport()
[all …]
/external/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c180 radeon_emit(cs, 0); in si_emit_compute()
181 radeon_emit(cs, 0); in si_emit_compute()
182 radeon_emit(cs, 0); in si_emit_compute()
186 radeon_emit(cs, 0); in si_emit_compute()
188 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
189 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff)); in si_emit_compute()
195 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) | in si_emit_compute()
197 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) | in si_emit_compute()
342 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_emit_config()
343 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1)); in si_emit_config()
[all …]
Dradv_cs.h47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
54 radeon_emit(cs, value); in radeon_set_config_reg()
62 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
69 radeon_emit(cs, value); in radeon_set_context_reg()
79 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
80 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
81 radeon_emit(cs, value); in radeon_set_context_reg_idx()
89 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
[all …]
Dradv_cmd_buffer.c403 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); in radv_emit_write_data_packet()
404 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) | in radv_emit_write_data_packet()
407 radeon_emit(cs, va); in radv_emit_write_data_packet()
408 radeon_emit(cs, va >> 32); in radv_emit_write_data_packet()
427 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in radv_cmd_buffer_trace_emit()
428 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id)); in radv_cmd_buffer_trace_emit()
536 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */ in radv_emit_graphics_blend_state()
537 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */ in radv_emit_graphics_blend_state()
538 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */ in radv_emit_graphics_blend_state()
588 radeon_emit(cmd_buffer->cs, va); in radv_emit_userdata_address()
[all …]
Dradv_query.c971 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in radv_CmdCopyQueryPoolResults()
972 radeon_emit(cs, 5 | WAIT_REG_MEM_MEM_SPACE(1)); in radv_CmdCopyQueryPoolResults()
973 radeon_emit(cs, src_va); in radv_CmdCopyQueryPoolResults()
974 radeon_emit(cs, src_va >> 32); in radv_CmdCopyQueryPoolResults()
975 radeon_emit(cs, 0x80000000); /* reference value */ in radv_CmdCopyQueryPoolResults()
976 radeon_emit(cs, 0xffffffff); /* mask */ in radv_CmdCopyQueryPoolResults()
977 radeon_emit(cs, 4); /* poll interval */ in radv_CmdCopyQueryPoolResults()
1025 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_CmdCopyQueryPoolResults()
1026 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | in radv_CmdCopyQueryPoolResults()
1028 radeon_emit(cs, avail_va); in radv_CmdCopyQueryPoolResults()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h118 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
119 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
125 radeon_emit(cs, value); in radeon_set_config_reg()
132 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
133 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
139 radeon_emit(cs, value); in radeon_set_context_reg()
148 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
149 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
150 radeon_emit(cs, value); in radeon_set_context_reg_idx()
157 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
[all …]
Dr600_pipe_common.c78 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_gfx_write_event_eop()
79 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); in si_gfx_write_event_eop()
80 radeon_emit(cs, scratch->gpu_address); in si_gfx_write_event_eop()
81 radeon_emit(cs, scratch->gpu_address >> 32); in si_gfx_write_event_eop()
87 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0)); in si_gfx_write_event_eop()
88 radeon_emit(cs, op); in si_gfx_write_event_eop()
89 radeon_emit(cs, sel); in si_gfx_write_event_eop()
90 radeon_emit(cs, va); /* address lo */ in si_gfx_write_event_eop()
91 radeon_emit(cs, va >> 32); /* address hi */ in si_gfx_write_event_eop()
92 radeon_emit(cs, new_fence); /* immediate data lo */ in si_gfx_write_event_eop()
[all …]

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