/external/u-boot/drivers/video/ |
D | ivybridge_igd.c | 277 u32 reg32; in gma_pm_init_pre_vbios() local 293 reg32 = gtt_read(gtt_bar, 0x42004); in gma_pm_init_pre_vbios() 294 reg32 |= (1 << 14) | (1 << 15); in gma_pm_init_pre_vbios() 295 gtt_write(gtt_bar, 0x42004, reg32); in gma_pm_init_pre_vbios() 300 reg32 = gtt_read(gtt_bar, 0x45010); in gma_pm_init_pre_vbios() 301 reg32 |= (1 << 1) | (1 << 0); in gma_pm_init_pre_vbios() 302 gtt_write(gtt_bar, 0x45010, reg32); in gma_pm_init_pre_vbios() 306 reg32 = gtt_read(gtt_bar, 0x911c); in gma_pm_init_pre_vbios() 308 if (reg32 & (1 << 13)) { in gma_pm_init_pre_vbios() 318 if (reg32 & (1 << 13)) { in gma_pm_init_pre_vbios() [all …]
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D | broadwell_igd.c | 357 u32 reg32; in igd_setup_panel() local 360 reg32 = (plat->dp_hotplug[0] & 0x7) << 2; in igd_setup_panel() 361 reg32 |= (plat->dp_hotplug[1] & 0x7) << 10; in igd_setup_panel() 362 reg32 |= (plat->dp_hotplug[2] & 0x7) << 18; in igd_setup_panel() 363 gtt_write(priv, PCH_PORT_HOTPLUG, reg32); in igd_setup_panel() 366 reg32 = (plat->port_select & 0x3) << 30; in igd_setup_panel() 367 reg32 |= (plat->power_up_delay & 0x1fff) << 16; in igd_setup_panel() 368 reg32 |= (plat->power_backlight_on_delay & 0x1fff); in igd_setup_panel() 369 gtt_write(priv, PCH_PP_ON_DELAYS, reg32); in igd_setup_panel() 372 reg32 = (plat->power_down_delay & 0x1fff) << 16; in igd_setup_panel() [all …]
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/external/u-boot/arch/x86/cpu/broadwell/ |
D | sata.c | 43 u32 reg32; in broadwell_sata_init() local 62 dm_pci_read_config32(dev, 0x98, ®32); in broadwell_sata_init() 63 reg32 &= ~((1 << 31) | (1 << 30)); in broadwell_sata_init() 64 reg32 |= 1 << 23; in broadwell_sata_init() 65 reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ in broadwell_sata_init() 66 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init() 74 reg32 = 0x183; in broadwell_sata_init() 75 reg32 |= (plat->port_map ^ 0xf) << 24; in broadwell_sata_init() 76 reg32 |= (plat->devslp_mux & 1) << 15; in broadwell_sata_init() 77 dm_pci_write_config32(dev, 0x94, reg32); in broadwell_sata_init() [all …]
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D | pch.c | 109 u32 reg32; in pch_enable_ioapic() local 115 reg32 = io_apic_read(0x01); in pch_enable_ioapic() 118 reg32 &= ~0x00ff0000; in pch_enable_ioapic() 119 reg32 |= 0x00270000; in pch_enable_ioapic() 121 io_apic_write(0x01, reg32); in pch_enable_ioapic() 376 u32 reg32; in pch_cg_init() local 408 reg32 = readl(RCB_REG(CG)); in pch_cg_init() 410 reg32 &= ~(1 << 29); /* LPC Dynamic */ in pch_cg_init() 412 reg32 |= (1 << 29); /* LPC Dynamic */ in pch_cg_init() 413 reg32 |= 1 << 31; /* LP LPC */ in pch_cg_init() [all …]
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/external/u-boot/arch/x86/cpu/ivybridge/ |
D | sata.c | 20 u32 reg32; in common_sata_init() local 24 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; in common_sata_init() 25 dm_pci_write_config32(dev, IDE_CONFIG, reg32); in common_sata_init() 44 u32 reg32; in bd82x6x_sata_init() local 77 reg32 = readl(abar + 0x00); in bd82x6x_sata_init() 78 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ in bd82x6x_sata_init() 79 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ in bd82x6x_sata_init() 82 reg32 &= ~0x00f00000; in bd82x6x_sata_init() 83 reg32 |= (speed_support & 0x03) << 20; in bd82x6x_sata_init() 85 writel(reg32, abar + 0x00); in bd82x6x_sata_init() [all …]
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D | lpc.c | 31 u32 reg32; in pch_enable_apic() local 42 reg32 = readl(IO_APIC_DATA); in pch_enable_apic() 44 writel(reg32, IO_APIC_DATA); in pch_enable_apic() 47 reg32 = readl(IO_APIC_DATA); in pch_enable_apic() 48 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); in pch_enable_apic() 49 if (reg32 != (1 << 25)) { in pch_enable_apic() 58 reg32 = readl(IO_APIC_DATA); in pch_enable_apic() 59 debug(" 0x%08x\n", reg32); in pch_enable_apic() 133 u32 reg32; in pch_power_options() local 223 reg32 = inl(pmbase + 0x04); /* PM1_CNT */ in pch_power_options() [all …]
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/external/u-boot/board/tqc/tqm834x/ |
D | pci.c | 56 u32 reg32; in pci_init_board() local 68 reg32 = OCCR_PCICOE1; in pci_init_board() 71 reg32 = 0xff000000; in pci_init_board() 76 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); in pci_init_board() 78 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ in pci_init_board() 83 clk->occr = reg32; in pci_init_board()
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/external/u-boot/drivers/serial/ |
D | serial_lpuart.c | 382 struct lpuart_fsl_reg32 *reg32 = plat->reg; in lpuart_serial_pending() local 389 lpuart_read32(plat->flags, ®32->stat, &stat); in lpuart_serial_pending()
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/external/u-boot/drivers/bios_emulator/x86emu/ |
D | ops.c | 2218 u32 *reg32; in x86emuOp_xchg_word_AX_register() local 2220 reg32 = DECODE_RM_LONG_REGISTER(op1); in x86emuOp_xchg_word_AX_register() 2224 M.x86.R_EAX = *reg32; in x86emuOp_xchg_word_AX_register() 2225 *reg32 = tmp; in x86emuOp_xchg_word_AX_register() 3049 u32 *reg32; in x86emuOp_mov_word_register_IMM() local 3050 reg32 = DECODE_RM_LONG_REGISTER(op1); in x86emuOp_mov_word_register_IMM() 3054 *reg32 = srcval; in x86emuOp_mov_word_register_IMM()
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/external/elfutils/tests/ |
D | run-addrcfi.sh | 63 MMX reg32 (%mm3): undefined 110 MMX reg32 (%mm3): undefined 164 SSE reg32 (%xmm15): undefined 230 SSE reg32 (%xmm15): undefined 334 FPU reg32 (f0): undefined 1356 FPU reg32 (f0): undefined 2384 FPU reg32 (f0): undefined 3410 control reg32 (%c0): undefined 3487 control reg32 (%c0): undefined 3717 SSE reg32 (%xmm15): undefined
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/external/syzkaller/pkg/ifuzz/gen/ |
D | all-enc-instructions.txt | 15569 # LZCNT reg32, reg/mem32 F30FBD /r 24968 # LZCNT reg32, reg/mem32 F30FBD /r
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