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Searched refs:s33 (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dcall-preserved-registers.ll8 ; GCN: s_mov_b32 s33, s7
12 ; GCN-NEXT: s_mov_b32 s4, s33
13 ; GCN-NEXT: s_mov_b32 s32, s33
16 ; GCN-NEXT: s_mov_b32 s4, s33
28 ; GCN: v_writelane_b32 v32, s33, 0
34 ; GCN: s_mov_b32 s33, s5
36 ; GCN-NEXT: s_mov_b32 s5, s33
37 ; GCN-NEXT: s_mov_b32 s33, s5
41 ; GCN-NEXT: s_mov_b32 s5, s33
46 ; GCN: v_readlane_b32 s33, v32, 0
[all …]
Dcall-argument-types.ll78 ; MESA: s_mov_b32 s33, s3{{$}}
79 ; HSA: s_mov_b32 s33, s9{{$}}
85 ; HSA-NEXT: s_mov_b32 s4, s33
86 ; HSA-NEXT: s_mov_b32 s32, s33
88 ; MESA-DAG: s_mov_b32 s4, s33{{$}}
89 ; MESA-DAG: s_mov_b32 s32, s33{{$}}
103 ; MESA: s_mov_b32 s33, s3{{$}}
110 ; GCN-DAG: s_mov_b32 s4, s33{{$}}
111 ; GCN-DAG: s_mov_b32 s32, s33{{$}}
124 ; MESA-DAG: s_mov_b32 s33, s3{{$}}
[all …]
Dcallee-special-input-sgprs.ll201 ; GCN: s_mov_b32 s33, s7
203 ; GCN: s_mov_b32 s4, s33
205 ; GCN: s_mov_b32 s32, s33
217 ; GCN: s_mov_b32 s33, s8
218 ; GCN-DAG: s_mov_b32 s4, s33
220 ; GCN: s_mov_b32 s32, s33
232 ; GCN: s_mov_b32 s33, s8
233 ; GCN-DAG: s_mov_b32 s4, s33
246 ; GCN: s_mov_b32 s33, s8
249 ; GCN: s_mov_b32 s4, s33
[all …]
Dcallee-frame-setup.ll42 ; GCN-DAG: v_writelane_b32 v32, s33,
48 ; GCN-DAG: s_mov_b32 s33, s5
52 ; GCN: s_mov_b32 s5, s33
55 ; GCN-DAG: v_readlane_b32 s33,
76 ; GCN-DAG: v_writelane_b32 v32, s33, 0
78 ; GCN: s_mov_b32 s33, s5
80 ; GCN: s_mov_b32 s5, s33
83 ; GCN-DAG: v_readlane_b32 s33, v32, 0
Dbyval-frame-setup.ll132 ; GCN: s_mov_b32 s33, s7
133 ; GCN: s_add_u32 s32, s33, 0xc00{{$}}
137 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s33 offset:8
138 ; GCN: buffer_store_dword [[THIRTEEN]], off, s[0:3], s33 offset:24
142 ; GCN-DAG: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s33 offset:8
143 ; GCN-DAG: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s33 offset:12
144 ; GCN-DAG: buffer_load_dword [[LOAD2:v[0-9]+]], off, s[0:3], s33 offset:16
145 ; GCN-DAG: buffer_load_dword [[LOAD3:v[0-9]+]], off, s[0:3], s33 offset:20
152 ; GCN-DAG: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s33 offset:24
153 ; GCN-DAG: buffer_load_dword [[LOAD5:v[0-9]+]], off, s[0:3], s33 offset:28
[all …]
Dnested-calls.ll16 ; GCN-DAG: v_writelane_b32 v32, s33, 0
24 ; GCN: v_readlane_b32 s33, v32, 0
Dcallee-special-input-vgprs.ll291 ; GCN: s_mov_b32 s33, s7
292 ; GCN: s_mov_b32 s32, s33
294 ; GCN: s_mov_b32 s4, s33
425 ; GCN: s_mov_b32 s33, s7
426 ; GCN: s_add_u32 s32, s33, 0x400{{$}}
430 ; GCN: buffer_store_dword [[K]], off, s[0:3], s33 offset:4
433 ; GCN: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s33 offset:4
551 ; GCN: s_mov_b32 s33, s7
552 ; GCN: s_mov_b32 s32, s33
646 ; GCN: s_mov_b32 s33, s7
[all …]
Dcall-graph-register-usage.ll16 ; GCN: v_writelane_b32 v32, s33, 0
22 ; GCN: v_readlane_b32 s33, v32, 0
Dbranch-relax-spill.ll43 %sgpr33 = tail call i32 asm sideeffect "s_mov_b32 s33, 0", "={s33}"() #0
162 tail call void asm sideeffect "; reg use $0", "{s33}"(i32 %sgpr33) #0
Dsibling-call.ll214 ; GCN-DAG: v_writelane_b32 v34, s33, 0
226 ; GCN-DAG: v_readlane_b32 s33, v34, 0
Dpartial-sgpr-to-vgpr-spills.ll123 ; GCN-NEXT: v_writelane_b32 v1, s33, 21
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvop1.txt117 # CHECK: v_frexp_exp_i32_f32_e32 v123, s33 ; encoding: [0x21,0x66,0xf6,0x7e]
120 # CHECK: v_frexp_mant_f32_e32 v123, s33 ; encoding: [0x21,0x68,0xf6,0x7e]
123 # CHECK: v_movreld_b32_e32 v123, s33 ; encoding: [0x21,0x6c,0xf6,0x7e]
126 # CHECK: v_movrels_b32_e32 v123, s33 ; encoding: [0x21,0x6e,0xf6,0x7e]
129 # CHECK: v_movrelsd_b32_e32 v123, s33 ; encoding: [0x21,0x70,0xf6,0x7e]
159 # CHECK: v_cvt_f64_f32_e32 v[222:223], s33 ; encoding: [0x21,0x20,0xbc,0x7f]
162 # CHECK: v_cvt_f64_u32_e32 v[222:223], s33 ; encoding: [0x21,0x2c,0xbc,0x7f]
201 # CHECK: v_log_f16_e32 v123, s33 ; encoding: [0x21,0x80,0xf6,0x7e]
219 # CHECK: v_trunc_f16_e32 v123, s33 ; encoding: [0x21,0x8c,0xf6,0x7e]
222 # CHECK: v_rndne_f16_e32 v123, s33 ; encoding: [0x21,0x8e,0xf6,0x7e]
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop1.txt117 # CHECK: v_frexp_exp_i32_f32_e32 v123, s33 ; encoding: [0x21,0x66,0xf6,0x7e]
120 # CHECK: v_frexp_mant_f32_e32 v123, s33 ; encoding: [0x21,0x68,0xf6,0x7e]
123 # CHECK: v_movreld_b32_e32 v123, s33 ; encoding: [0x21,0x6c,0xf6,0x7e]
126 # CHECK: v_movrels_b32_e32 v123, s33 ; encoding: [0x21,0x6e,0xf6,0x7e]
129 # CHECK: v_movrelsd_b32_e32 v123, s33 ; encoding: [0x21,0x70,0xf6,0x7e]
159 # CHECK: v_cvt_f64_f32_e32 v[222:223], s33 ; encoding: [0x21,0x20,0xbc,0x7f]
162 # CHECK: v_cvt_f64_u32_e32 v[222:223], s33 ; encoding: [0x21,0x2c,0xbc,0x7f]
201 # CHECK: v_log_f16_e32 v123, s33 ; encoding: [0x21,0x80,0xf6,0x7e]
219 # CHECK: v_trunc_f16_e32 v123, s33 ; encoding: [0x21,0x8c,0xf6,0x7e]
222 # CHECK: v_rndne_f16_e32 v123, s33 ; encoding: [0x21,0x8e,0xf6,0x7e]
[all …]
/external/clang/test/CodeGen/
Darm-arguments.c177 struct s33 { char buf[32*32]; }; struct
178 void f33(struct s33 s) { } in f33()
Darm-aapcs-vfp.c122 struct s33 { char buf[32*32]; }; argument
123 void f33(struct s33 s) { } in f33()
Darm64-arguments.c129 struct s33 { char buf[32*32]; }; struct
130 void f33(struct s33 s) { } in f33()
Dx86_32-arguments-darwin.c139 struct s33 { float a; long long : 0; } f33(void) { while (1) {} } in f33() argument
/external/v8/benchmarks/
Dregexp.js214 var s33 = computeInputVariants('Pbhagel=IIZ=', 78);
251 re8.exec(s33[i]);