1; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s 2 3; FIXME: we should disable sdwa peephole because dead-code elimination, that 4; runs after peephole, ruins this test (different register numbers) 5 6; Spill all SGPRs so multiple VGPRs are required for spilling all of them. 7 8; Ideally we only need 2 VGPRs for all spilling. The VGPRs are 9; allocated per-frame index, so it's possible to get up with more. 10 11; GCN-LABEL: {{^}}spill_sgprs_to_multiple_vgprs: 12 13; GCN: def s[4:11] 14; GCN: def s[12:19] 15; GCN: def s[20:27] 16; GCN: def s[28:35] 17; GCN: def s[36:43] 18; GCN: def s[44:51] 19; GCN: def s[52:59] 20; GCN: def s[60:67] 21; GCN: def s[68:75] 22; GCN: def s[76:83] 23; GCN: def s[84:91] 24 25; GCN: v_writelane_b32 v0, s4, 0 26; GCN-NEXT: v_writelane_b32 v0, s5, 1 27; GCN-NEXT: v_writelane_b32 v0, s6, 2 28; GCN-NEXT: v_writelane_b32 v0, s7, 3 29; GCN-NEXT: v_writelane_b32 v0, s8, 4 30; GCN-NEXT: v_writelane_b32 v0, s9, 5 31; GCN-NEXT: v_writelane_b32 v0, s10, 6 32; GCN-NEXT: v_writelane_b32 v0, s11, 7 33 34; GCN: def s{{\[}}[[TMP_LO:[0-9]+]]:[[TMP_HI:[0-9]+]]{{\]}} 35; GCN: v_writelane_b32 v0, s[[TMP_LO]], 8 36; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 9 37; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 10 38; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 11 39; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 12 40; GCN-NEXT: v_writelane_b32 v0, s9, 13 41; GCN-NEXT: v_writelane_b32 v0, s10, 14 42; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 15 43 44; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}} 45; GCN: v_writelane_b32 v0, s[[TMP_LO]], 16 46; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 17 47; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 18 48; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 19 49; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 20 50; GCN-NEXT: v_writelane_b32 v0, s9, 21 51; GCN-NEXT: v_writelane_b32 v0, s10, 22 52; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 23 53 54; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}} 55; GCN: v_writelane_b32 v0, s[[TMP_LO]], 24 56; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 25 57; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 26 58; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 27 59; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 28 60; GCN-NEXT: v_writelane_b32 v0, s9, 29 61; GCN-NEXT: v_writelane_b32 v0, s10, 30 62; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 31 63 64; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}} 65; GCN: v_writelane_b32 v0, s[[TMP_LO]], 32 66; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 33 67; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 34 68; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 35 69; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 36 70; GCN-NEXT: v_writelane_b32 v0, s9, 37 71; GCN-NEXT: v_writelane_b32 v0, s10, 38 72; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 39 73 74; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}} 75; GCN: v_writelane_b32 v0, s[[TMP_LO]], 40 76; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 41 77; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 42 78; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 43 79; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 44 80; GCN-NEXT: v_writelane_b32 v0, s9, 45 81; GCN-NEXT: v_writelane_b32 v0, s10, 46 82; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 47 83 84; GCN: def s{{\[}}[[TMP_LO]]:[[TMP_HI]]{{\]}} 85; GCN: v_writelane_b32 v0, s[[TMP_LO]], 48 86; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 49 87; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 50 88; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 51 89; GCN-NEXT: v_writelane_b32 v0, s{{[0-9]+}}, 52 90; GCN-NEXT: v_writelane_b32 v0, s9, 53 91; GCN-NEXT: v_writelane_b32 v0, s10, 54 92; GCN-NEXT: v_writelane_b32 v0, s[[TMP_HI]], 55 93 94; GCN-NEXT: v_writelane_b32 v0, s84, 56 95; GCN-NEXT: v_writelane_b32 v0, s85, 57 96; GCN-NEXT: v_writelane_b32 v0, s86, 58 97; GCN-NEXT: v_writelane_b32 v0, s87, 59 98; GCN-NEXT: v_writelane_b32 v0, s88, 60 99; GCN-NEXT: v_writelane_b32 v0, s89, 61 100; GCN-NEXT: v_writelane_b32 v0, s90, 62 101; GCN-NEXT: v_writelane_b32 v0, s91, 63 102; GCN-NEXT: v_writelane_b32 v1, s12, 0 103; GCN-NEXT: v_writelane_b32 v1, s13, 1 104; GCN-NEXT: v_writelane_b32 v1, s14, 2 105; GCN-NEXT: v_writelane_b32 v1, s15, 3 106; GCN-NEXT: v_writelane_b32 v1, s16, 4 107; GCN-NEXT: v_writelane_b32 v1, s17, 5 108; GCN-NEXT: v_writelane_b32 v1, s18, 6 109; GCN-NEXT: v_writelane_b32 v1, s19, 7 110; GCN-NEXT: v_writelane_b32 v1, s20, 8 111; GCN-NEXT: v_writelane_b32 v1, s21, 9 112; GCN-NEXT: v_writelane_b32 v1, s22, 10 113; GCN-NEXT: v_writelane_b32 v1, s23, 11 114; GCN-NEXT: v_writelane_b32 v1, s24, 12 115; GCN-NEXT: v_writelane_b32 v1, s25, 13 116; GCN-NEXT: v_writelane_b32 v1, s26, 14 117; GCN-NEXT: v_writelane_b32 v1, s27, 15 118; GCN-NEXT: v_writelane_b32 v1, s28, 16 119; GCN-NEXT: v_writelane_b32 v1, s29, 17 120; GCN-NEXT: v_writelane_b32 v1, s30, 18 121; GCN-NEXT: v_writelane_b32 v1, s31, 19 122; GCN-NEXT: v_writelane_b32 v1, s32, 20 123; GCN-NEXT: v_writelane_b32 v1, s33, 21 124; GCN-NEXT: v_writelane_b32 v1, s34, 22 125; GCN-NEXT: v_writelane_b32 v1, s35, 23 126; GCN-NEXT: v_writelane_b32 v1, s36, 24 127; GCN-NEXT: v_writelane_b32 v1, s37, 25 128; GCN-NEXT: v_writelane_b32 v1, s38, 26 129; GCN-NEXT: v_writelane_b32 v1, s39, 27 130; GCN-NEXT: v_writelane_b32 v1, s40, 28 131; GCN-NEXT: v_writelane_b32 v1, s41, 29 132; GCN-NEXT: v_writelane_b32 v1, s42, 30 133; GCN-NEXT: v_writelane_b32 v1, s43, 31 134; GCN-NEXT: v_writelane_b32 v1, s44, 32 135; GCN-NEXT: v_writelane_b32 v1, s45, 33 136; GCN-NEXT: v_writelane_b32 v1, s46, 34 137; GCN-NEXT: v_writelane_b32 v1, s47, 35 138; GCN-NEXT: v_writelane_b32 v1, s48, 36 139; GCN-NEXT: v_writelane_b32 v1, s49, 37 140; GCN-NEXT: v_writelane_b32 v1, s50, 38 141; GCN-NEXT: v_writelane_b32 v1, s51, 39 142; GCN-NEXT: v_writelane_b32 v1, s52, 40 143; GCN-NEXT: v_writelane_b32 v1, s53, 41 144; GCN-NEXT: v_writelane_b32 v1, s54, 42 145; GCN-NEXT: v_writelane_b32 v1, s55, 43 146; GCN-NEXT: v_writelane_b32 v1, s56, 44 147; GCN-NEXT: v_writelane_b32 v1, s57, 45 148; GCN-NEXT: v_writelane_b32 v1, s58, 46 149; GCN-NEXT: v_writelane_b32 v1, s59, 47 150; GCN-NEXT: v_writelane_b32 v1, s60, 48 151; GCN-NEXT: v_writelane_b32 v1, s61, 49 152; GCN-NEXT: v_writelane_b32 v1, s62, 50 153; GCN-NEXT: v_writelane_b32 v1, s63, 51 154; GCN-NEXT: v_writelane_b32 v1, s64, 52 155; GCN-NEXT: v_writelane_b32 v1, s65, 53 156; GCN-NEXT: v_writelane_b32 v1, s66, 54 157; GCN-NEXT: v_writelane_b32 v1, s67, 55 158; GCN-NEXT: v_writelane_b32 v1, s68, 56 159; GCN-NEXT: v_writelane_b32 v1, s69, 57 160; GCN-NEXT: v_writelane_b32 v1, s70, 58 161; GCN-NEXT: v_writelane_b32 v1, s71, 59 162; GCN-NEXT: v_writelane_b32 v1, s72, 60 163; GCN-NEXT: v_writelane_b32 v1, s73, 61 164; GCN-NEXT: v_writelane_b32 v1, s74, 62 165; GCN-NEXT: v_writelane_b32 v1, s75, 63 166; GCN-NEXT: v_writelane_b32 v2, s76, 0 167; GCN-NEXT: v_writelane_b32 v2, s77, 1 168; GCN-NEXT: v_writelane_b32 v2, s78, 2 169; GCN-NEXT: v_writelane_b32 v2, s79, 3 170; GCN-NEXT: v_writelane_b32 v2, s80, 4 171; GCN-NEXT: v_writelane_b32 v2, s81, 5 172; GCN-NEXT: v_writelane_b32 v2, s82, 6 173; GCN-NEXT: v_writelane_b32 v2, s83, 7 174; GCN: s_cbranch_scc1 175 176 177; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v0, 0 178; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 1 179; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 2 180; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 3 181; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 4 182; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 5 183; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 6 184; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v0, 7 185; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 186 187 188; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 0 189; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 1 190; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 2 191; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 3 192; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 4 193; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 5 194; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 6 195; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 7 196; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 197 198; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 8 199; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 9 200; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 10 201; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 11 202; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 12 203; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 13 204; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 14 205; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 15 206; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 207 208; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 16 209; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 17 210; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 18 211; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 19 212; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 20 213; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 21 214; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 22 215; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 23 216; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 217 218; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 24 219; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 25 220; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 26 221; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 27 222; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 28 223; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 29 224; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 30 225; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 31 226; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 227 228; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 32 229; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 33 230; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 34 231; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 35 232; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 36 233; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 37 234; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 38 235; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 39 236; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 237 238; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 40 239; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 41 240; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 42 241; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 43 242; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 44 243; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 45 244; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 46 245; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 47 246; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 247 248; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 48 249; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 49 250; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 50 251; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 51 252; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 52 253; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 53 254; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 54 255; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 55 256; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 257 258; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 56 259; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 57 260; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 58 261; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 59 262; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 60 263; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 61 264; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 62 265; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI]], v1, 63 266; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 267 268; GCN: v_readlane_b32 s{{[0-9]+}}, v2, 0 269; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 1 270; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 2 271; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 3 272; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 4 273; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 5 274; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 6 275; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v2, 7 276; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 277 278; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 56 279; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 57 280; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 58 281; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 59 282; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 60 283; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 61 284; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 62 285; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 63 286; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 287 288; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 8 289; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 9 290; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 10 291; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 11 292; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 12 293; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 13 294; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 14 295; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 15 296; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 297 298; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 16 299; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 17 300; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 18 301; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 19 302; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 20 303; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 21 304; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 22 305; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 23 306; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 307 308; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 24 309; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 25 310; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 26 311; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 27 312; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 28 313; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 29 314; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 30 315; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 31 316; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 317 318; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 32 319; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 33 320; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 34 321; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 35 322; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 36 323; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 37 324; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 38 325; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 39 326; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 327 328; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 40 329; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 41 330; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 42 331; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 43 332; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 44 333; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 45 334; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 46 335; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 47 336; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 337 338; GCN: v_readlane_b32 s{{[0-9]+}}, v0, 48 339; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 49 340; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 50 341; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 51 342; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 52 343; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 53 344; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 54 345; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 55 346; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 347define amdgpu_kernel void @spill_sgprs_to_multiple_vgprs(i32 addrspace(1)* %out, i32 %in) #0 { 348 %wide.sgpr0 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 349 %wide.sgpr1 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 350 %wide.sgpr2 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 351 %wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 352 %wide.sgpr4 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 353 %wide.sgpr5 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 354 %wide.sgpr6 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 355 %wide.sgpr7 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 356 %wide.sgpr8 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 357 %wide.sgpr9 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 358 %wide.sgpr10 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 359 %wide.sgpr11 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 360 %wide.sgpr12 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 361 %wide.sgpr13 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 362 %wide.sgpr14 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 363 %wide.sgpr15 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 364 %wide.sgpr16 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 365 %cmp = icmp eq i32 %in, 0 366 br i1 %cmp, label %bb0, label %ret 367 368bb0: 369 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr0) #0 370 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr1) #0 371 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr2) #0 372 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr3) #0 373 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr4) #0 374 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr5) #0 375 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr6) #0 376 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr7) #0 377 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr8) #0 378 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr9) #0 379 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr10) #0 380 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr11) #0 381 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr12) #0 382 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr13) #0 383 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr14) #0 384 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr15) #0 385 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr16) #0 386 br label %ret 387 388ret: 389 ret void 390} 391 392; Some of the lanes of an SGPR spill are in one VGPR and some forced 393; into the next available VGPR. 394 395; GCN-LABEL: {{^}}split_sgpr_spill_2_vgprs: 396; GCN: def s[4:19] 397; GCN: def s[20:35] 398 399; GCN: v_writelane_b32 v0, s4, 50 400; GCN-NEXT: v_writelane_b32 v0, s5, 51 401; GCN-NEXT: v_writelane_b32 v0, s6, 52 402; GCN-NEXT: v_writelane_b32 v0, s7, 53 403; GCN-NEXT: v_writelane_b32 v0, s8, 54 404; GCN-NEXT: v_writelane_b32 v0, s9, 55 405; GCN-NEXT: v_writelane_b32 v0, s10, 56 406; GCN-NEXT: v_writelane_b32 v0, s11, 57 407; GCN-NEXT: v_writelane_b32 v0, s12, 58 408; GCN-NEXT: v_writelane_b32 v0, s13, 59 409; GCN-NEXT: v_writelane_b32 v0, s14, 60 410; GCN-NEXT: v_writelane_b32 v0, s15, 61 411; GCN-NEXT: v_writelane_b32 v0, s16, 62 412; GCN-NEXT: v_writelane_b32 v0, s17, 63 413; GCN-NEXT: v_writelane_b32 v1, s18, 0 414; GCN-NEXT: v_writelane_b32 v1, s19, 1 415 416; GCN: v_readlane_b32 s4, v0, 50 417; GCN-NEXT: v_readlane_b32 s5, v0, 51 418; GCN-NEXT: v_readlane_b32 s6, v0, 52 419; GCN-NEXT: v_readlane_b32 s7, v0, 53 420; GCN-NEXT: v_readlane_b32 s8, v0, 54 421; GCN-NEXT: v_readlane_b32 s9, v0, 55 422; GCN-NEXT: v_readlane_b32 s10, v0, 56 423; GCN-NEXT: v_readlane_b32 s11, v0, 57 424; GCN-NEXT: v_readlane_b32 s12, v0, 58 425; GCN-NEXT: v_readlane_b32 s13, v0, 59 426; GCN-NEXT: v_readlane_b32 s14, v0, 60 427; GCN-NEXT: v_readlane_b32 s15, v0, 61 428; GCN-NEXT: v_readlane_b32 s16, v0, 62 429; GCN-NEXT: v_readlane_b32 s17, v0, 63 430; GCN-NEXT: v_readlane_b32 s18, v1, 0 431; GCN-NEXT: v_readlane_b32 s19, v1, 1 432define amdgpu_kernel void @split_sgpr_spill_2_vgprs(i32 addrspace(1)* %out, i32 %in) #1 { 433 %wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 434 %wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 435 %wide.sgpr2 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 436 %wide.sgpr5 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 437 %wide.sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0 438 %wide.sgpr4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0 439 440 %cmp = icmp eq i32 %in, 0 441 br i1 %cmp, label %bb0, label %ret 442 443bb0: 444 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr0) #0 445 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr1) #0 446 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr2) #0 447 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr3) #0 448 call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr4) #0 449 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr5) #0 450 br label %ret 451 452ret: 453 ret void 454} 455 456; The first 64 SGPR spills can go to a VGPR, but there isn't a second 457; so some spills must be to memory. The last 16 element spill runs out of lanes at the 15th element. 458 459; GCN-LABEL: {{^}}no_vgprs_last_sgpr_spill: 460 461; GCN: v_writelane_b32 v23, s{{[0-9]+}}, 0 462; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 1 463; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 2 464; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 3 465; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 4 466; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 5 467; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 6 468; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 7 469; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 8 470; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 9 471; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 10 472; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 11 473; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 12 474; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 13 475; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 14 476; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 15 477 478; GCN: v_writelane_b32 v23, s{{[0-9]+}}, 16 479; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 17 480; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 18 481; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 19 482; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 20 483; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 21 484; GCN-NEXT: v_writelane_b32 v23, s{{[0-9]+}}, 22 485; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 23 486; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 24 487; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 25 488; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 26 489; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 27 490; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 28 491; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 29 492; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 30 493; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 31 494 495; GCN: def s[0:1] 496; GCN: v_writelane_b32 v23, s0, 32 497; GCN-NEXT: v_writelane_b32 v23, s1, 33 498 499; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 34 500; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 35 501; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 36 502; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 37 503; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 38 504; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 39 505; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 40 506; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 41 507; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 42 508; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 43 509; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 44 510; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 45 511; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 46 512; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 47 513; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 48 514; GCN-NEXT: v_writelane_b32 v23, s{{[[0-9]+}}, 49 515 516; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 517; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 518; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 519; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 520; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 521; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 522; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 523; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 524; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 525; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 526; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 527; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 528; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 529; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 530; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 531; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 532; GCN: s_cbranch_scc1 533 534 535; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v23, 0 536; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 1 537; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 2 538; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 3 539; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 4 540; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 5 541; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 6 542; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 7 543; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 8 544; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 9 545; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 10 546; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 11 547; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 12 548; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 13 549; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 14 550; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v23, 15 551; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 552 553 554; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v23, 34 555; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 35 556; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 36 557; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 37 558; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 38 559; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 39 560; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 40 561; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 41 562; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 42 563; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 43 564; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 44 565; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 45 566; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 46 567; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 47 568; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 48 569; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v23, 49 570; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 571 572; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v23, 16 573; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 17 574; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 18 575; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 19 576; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 20 577; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 21 578; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 22 579; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 23 580; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 24 581; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 25 582; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 26 583; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 27 584; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 28 585; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 29 586; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v23, 30 587; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v23, 31 588; GCN: ; use s{{\[}}[[USE_TMP_LO]]:[[USE_TMP_HI]]{{\]}} 589 590; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 591; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 592; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 593; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 594; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 595; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 596; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 597; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 598; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 599; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 600; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 601; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 602; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 603; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 604; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 605; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 606 607; GCN: v_readlane_b32 s0, v23, 32 608; GCN: v_readlane_b32 s1, v23, 33 609; GCN: ;;#ASMSTART 610; GCN: ; use s[0:1] 611define amdgpu_kernel void @no_vgprs_last_sgpr_spill(i32 addrspace(1)* %out, i32 %in) #1 { 612 call void asm sideeffect "", "~{v[0:7]}" () #0 613 call void asm sideeffect "", "~{v[8:15]}" () #0 614 call void asm sideeffect "", "~{v[16:19]}"() #0 615 call void asm sideeffect "", "~{v[20:21]}"() #0 616 call void asm sideeffect "", "~{v22}"() #0 617 618 %wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 619 %wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 620 %wide.sgpr2 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 621 %wide.sgpr3 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0 622 %wide.sgpr4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0 623 %cmp = icmp eq i32 %in, 0 624 br i1 %cmp, label %bb0, label %ret 625 626bb0: 627 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr0) #0 628 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr1) #0 629 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr2) #0 630 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr3) #0 631 call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr4) #0 632 br label %ret 633 634ret: 635 ret void 636} 637 638attributes #0 = { nounwind } 639attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" } 640