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Searched refs:s_mov_b32 (Results 1 – 25 of 219) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
Dllvm.amdgcn.sendmsg.ll5 ; GCN: s_mov_b32 m0, 0
6 ; GCN-NOT: s_mov_b32 m0
15 ; GCN: s_mov_b32 m0, 0
16 ; GCN-NOT: s_mov_b32 m0
25 ; GCN: s_mov_b32 m0, 0
26 ; GCN-NOT: s_mov_b32 m0
35 ; GCN: s_mov_b32 m0, 0
36 ; GCN-NOT: s_mov_b32 m0
45 ; GCN: s_mov_b32 m0, 0
46 ; GCN-NOT: s_mov_b32 m0
[all …]
Dlarge-alloca-graphics.ll6 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
7 ; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
8 ; GCN-DAG: s_mov_b32 s10, -1
9 ; CI-DAG: s_mov_b32 s11, 0xe8f000
10 ; VI-DAG: s_mov_b32 s11, 0xe80000
11 ; GFX9-DAG: s_mov_b32 s11, 0xe00000
28 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
29 ; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
30 ; GCN-DAG: s_mov_b32 s10, -1
31 ; CI-DAG: s_mov_b32 s11, 0xe8f000
[all …]
Dcallee-special-input-sgprs.ll118 ; GCN: s_mov_b32 s5, s32
201 ; GCN: s_mov_b32 s33, s7
203 ; GCN: s_mov_b32 s4, s33
205 ; GCN: s_mov_b32 s32, s33
217 ; GCN: s_mov_b32 s33, s8
218 ; GCN-DAG: s_mov_b32 s4, s33
219 ; GCN-DAG: s_mov_b32 s6, s7
220 ; GCN: s_mov_b32 s32, s33
232 ; GCN: s_mov_b32 s33, s8
233 ; GCN-DAG: s_mov_b32 s4, s33
[all …]
Dlocal-atomics64.ll6 ; SICIVI: s_mov_b32 m0
18 ; SICIVI: s_mov_b32 m0
31 ; SICIVI: s_mov_b32 m0
43 ; SICIVI-DAG: s_mov_b32 m0
62 ; SICIVI-DAG: s_mov_b32 m0
77 ; SICIVI: s_mov_b32 m0
90 ; SICIVI: s_mov_b32 m0
102 ; SICIVI: s_mov_b32 m0
115 ; SICIVI-DAG: s_mov_b32 m0
130 ; SICIVI: s_mov_b32 m0
[all …]
Dcall-preserved-registers.ll8 ; GCN: s_mov_b32 s33, s7
12 ; GCN-NEXT: s_mov_b32 s4, s33
13 ; GCN-NEXT: s_mov_b32 s32, s33
16 ; GCN-NEXT: s_mov_b32 s4, s33
34 ; GCN: s_mov_b32 s33, s5
36 ; GCN-NEXT: s_mov_b32 s5, s33
37 ; GCN-NEXT: s_mov_b32 s33, s5
41 ; GCN-NEXT: s_mov_b32 s5, s33
57 ; GCN: s_mov_b32 s33, s5
59 ; GCN-NEXT: s_mov_b32 s5, s33
[all …]
Dload-local-i1.ll7 ; SICIVI: s_mov_b32 m0
24 ; SICIVI: s_mov_b32 m0
33 ; SICIVI: s_mov_b32 m0
42 ; SICIVI: s_mov_b32 m0
51 ; SICIVI: s_mov_b32 m0
60 ; SICIVI: s_mov_b32 m0
69 ; SICIVI: s_mov_b32 m0
78 ; SICIVI: s_mov_b32 m0
87 ; SICIVI: s_mov_b32 m0
100 ; SICIVI: s_mov_b32 m0
[all …]
Dlocal-atomics.ll10 ; SICIVI-DAG: s_mov_b32 m0
26 ; SICIVI: s_mov_b32 m0
43 ; SICIVI-DAG: s_mov_b32 m0
59 ; SICIVI: s_mov_b32 m0
73 ; SICIVI: s_mov_b32 m0
92 ; SICIVI-DAG: s_mov_b32 m0
107 ; SICIVI-DAG: s_mov_b32 m0
121 ; SICIVI: s_mov_b32 m0
140 ; SICIVI: s_mov_b32 m0
154 ; SICIVI: s_mov_b32 m0
[all …]
Datomic_load_local.ll6 ; GFX9-NOT: s_mov_b32 m0
7 ; CI-NEXT: s_mov_b32 m0
18 ; GFX9-NOT: s_mov_b32 m0
19 ; CI-NEXT: s_mov_b32 m0
31 ; GFX9-NOT: s_mov_b32 m0
32 ; CI-NEXT: s_mov_b32 m0
43 ; GFX9-NOT: s_mov_b32 m0
44 ; CI-NEXT: s_mov_b32 m0
Datomic_store_local.ll6 ; GFX9-NOT: s_mov_b32 m0
7 ; CI-NEXT: s_mov_b32 m0
18 ; GFX9-NOT: s_mov_b32 m0
19 ; CI-NEXT: s_mov_b32 m0
31 ; GFX9-NOT: s_mov_b32 m0
32 ; CI-NEXT: s_mov_b32 m0
43 ; GFX9-NOT: s_mov_b32 m0
44 ; CI-NEXT: s_mov_b32 m0
Dconstant-address-space-32bit.ll7 ; GCN-DAG: s_mov_b32 s3, 0
8 ; GCN-DAG: s_mov_b32 s2, s1
9 ; GCN-DAG: s_mov_b32 s1, s3
24 ; GCN-DAG: s_mov_b32 s3, 0
25 ; GCN-DAG: s_mov_b32 s2, s1
26 ; GCN-DAG: s_mov_b32 s1, s3
41 ; GCN-DAG: s_mov_b32 s3, 0
42 ; GCN-DAG: s_mov_b32 s2, s1
43 ; GCN-DAG: s_mov_b32 s1, s3
58 ; GCN-DAG: s_mov_b32 s3, 0
[all …]
Dload-local-i32.ll13 ; SICIVI: s_mov_b32 m0, -1
26 ; SICIVI: s_mov_b32 m0, -1
38 ; SICIVI: s_mov_b32 m0, -1
51 ; SICIVI: s_mov_b32 m0, -1
64 ; SICIVI: s_mov_b32 m0, -1
77 ; SICIVI: s_mov_b32 m0, -1
96 ; SICIVI: s_mov_b32 m0, -1
107 ; SICIVI: s_mov_b32 m0, -1
118 ; SICIVI: s_mov_b32 m0, -1
129 ; SICIVI: s_mov_b32 m0, -1
[all …]
Dstore-local.ll8 ; SICIVI: s_mov_b32 m0
23 ; SICIVI: s_mov_b32 m0
37 ; SICIVI: s_mov_b32 m0
51 ; SICIVI: s_mov_b32 m0
66 ; SICIVI: s_mov_b32 m0
81 ; SICIVI: s_mov_b32 m0
107 ; SICIVI: s_mov_b32 m0
127 ; SICIVI: s_mov_b32 m0
146 ; SICIVI: s_mov_b32 m0
167 ; SICIVI: s_mov_b32 m0
[all …]
Dspill-m0.ll10 ; TOSMEM: s_mov_b32 s[[LO:[0-9]+]], SCRATCH_RSRC_DWORD0
11 ; TOSMEM: s_mov_b32 s[[HI:[0-9]+]], 0xe80000
15 ; TOVGPR-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
18 ; TOVMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
22 ; TOSMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
31 ; TOVGPR: s_mov_b32 m0, [[M0_RESTORE]]
36 ; TOVMEM: s_mov_b32 m0, [[M0_RESTORE]]
41 ; TOSMEM: s_mov_b32 m0, [[M0_RESTORE]]
46 %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={M0}"() #0
64 ; GCN: s_mov_b32 m0, s6
[all …]
Dlocal-64.ll7 ; SICIVI: s_mov_b32 m0
20 ; SICIVI: s_mov_b32 m0
32 ; SICIVI: s_mov_b32 m0
46 ; SICIVI-DAG: s_mov_b32 m0
67 ; SICIVI: s_mov_b32 m0
81 ; SICIVI: s_mov_b32 m0
93 ; SICIVI: s_mov_b32 m0
107 ; SICIVI: s_mov_b32 m0
119 ; SICIVI: s_mov_b32 m0
131 ; SICIVI: s_mov_b32 m0
[all …]
Dinline-constraints.ll35 ; GCN: s_mov_b32 m0, -1
36 ; GCN: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
39 %m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={M0}"()
45 ; GCN: s_mov_b32 [[REG:s[0-9]+]], 32
53 ; GCN: s_mov_b32 [[REG:s[0-9]+]], 1.0
62 ; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], -4{{$}}
63 ; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], -1{{$}}
71 ; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], 0{{$}}
72 ; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], 0x3ff00000{{$}}
Dwrite_register.ll40 ; CHECK: s_mov_b32 flat_scratch_lo, 0
41 ; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}}
50 ; CHECK: s_mov_b32 flat_scratch_hi, 0
51 ; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}}
60 ; CHECK: s_mov_b32 exec_lo, 0
61 ; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
70 ; CHECK: s_mov_b32 exec_hi, 0
71 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
/external/llvm/test/MC/AMDGPU/
Dsop1-err.s5 s_mov_b32 v1, s2 label
8 s_mov_b32 s1, v0 label
11 s_mov_b32 s[1:2], s0 label
14 s_mov_b32 s0, s[1:2] label
17 s_mov_b32 s220, s0 label
20 s_mov_b32 s0, s220 label
30 s_mov_b32 s1, 0xfffffffff label
41 s_mov_b32 s label
45 s_mov_b32 s102, 1 label
49 s_mov_b32 s103, 1 label
Dexpressions.s8 s_mov_b32 s0, global label
17 s_mov_b32 s0, gds label
22 s_mov_b32 s0, gds+4 label
35 s_mov_b32 s0, foo+2 label
40 s_mov_b32 s0, foo+2 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsop1-err.s5 s_mov_b32 v1, s2 label
8 s_mov_b32 s1, v0 label
11 s_mov_b32 s[1:2], s0 label
14 s_mov_b32 s0, s[1:2] label
17 s_mov_b32 s220, s0 label
20 s_mov_b32 s0, s220 label
30 s_mov_b32 s label
34 s_mov_b32 s102, 1 label
38 s_mov_b32 s103, 1 label
Dreloc.s28 s_mov_b32 s0, SCRATCH_RSRC_DWORD0
29 s_mov_b32 s1, SCRATCH_RSRC_DWORD1
30 s_mov_b32 s2, global_var0@GOTPCREL
31 s_mov_b32 s3, global_var1@gotpcrel32@lo
32 s_mov_b32 s4, global_var2@gotpcrel32@hi
33 s_mov_b32 s5, global_var3@rel32@lo
34 s_mov_b32 s6, global_var4@rel32@hi
Dexpressions.s8 s_mov_b32 s0, global label
17 s_mov_b32 s0, gds label
22 s_mov_b32 s0, gds+4 label
35 s_mov_b32 s0, foo+2 label
40 s_mov_b32 s0, foo+2 label
/external/llvm/test/CodeGen/AMDGPU/
Dlarge-alloca-graphics.ll5 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
6 ; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
7 ; GCN-DAG: s_mov_b32 s10, -1
8 ; CI-DAG: s_mov_b32 s11, 0xe8f000
9 ; VI-DAG: s_mov_b32 s11, 0xe80000
26 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
27 ; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
28 ; GCN-DAG: s_mov_b32 s10, -1
29 ; CI-DAG: s_mov_b32 s11, 0xe8f000
30 ; VI-DAG: s_mov_b32 s11, 0xe80000
Dwrite_register.ll37 ; CHECK: s_mov_b32 flat_scratch_lo, 0
38 ; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}}
46 ; CHECK: s_mov_b32 flat_scratch_hi, 0
47 ; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}}
55 ; CHECK: s_mov_b32 exec_lo, 0
56 ; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
64 ; CHECK: s_mov_b32 exec_hi, 0
65 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
Dconcat_vectors.ll9 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
18 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
27 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
36 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
45 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
54 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
63 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
72 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
81 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
90 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
[all …]

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