/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | SMInstructions.td | 60 bits<7> sbase; 67 : SM_Pseudo<opName, (outs), ins, " $sdata, $sbase, $offset"> { 97 : SM_Pseudo<opName, (outs), ins, " $sbase, $offset"> { 113 (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc), 114 " $sdst, $sbase, $offset$glc", []> { 123 (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc), 124 " $sdst, $sbase, $offset$glc", []> { 135 (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc), 136 " $sdata, $sbase, $offset$glc", []> { 144 (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc), [all …]
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D | SILoadStoreOptimizer.cpp | 323 AddrOpName[NumAddresses++] = AMDGPU::OpName::sbase; in findMatchingInst() 652 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) in mergeSBufferLoadImmPair()
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D | SIInstrInfo.cpp | 191 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 || in areLoadsFromSameBasePtr() 192 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) in areLoadsFromSameBasePtr() 350 getNamedOperand(LdSt, AMDGPU::OpName::sbase); in getMemOpBaseRegImmOfs() 3439 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase); in legalizeOperandsSMRD() 3961 .add(*getNamedOperand(Inst, AMDGPU::OpName::sbase)) // srsrc in moveToVALU() 5011 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sbase); in isBufferSMRD()
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/external/iproute2/ip/ |
D | ifcfg | 4 local sbase fwd 5 sbase=/proc/sys/net/ipv4/conf 7 if [ -d $sbase ]; then 8 for dir in $sbase/*/forwarding; do
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/external/u-boot/drivers/spi/ |
D | ich.c | 118 void *sbase; in ich_init_controller() local 122 sbase = (void *)sbase_addr; in ich_init_controller() 123 debug("%s: sbase=%p\n", __func__, sbase); in ich_init_controller() 126 struct ich7_spi_regs *ich7_spi = sbase; in ich_init_controller() 140 struct ich9_spi_regs *ich9_spi = sbase; in ich_init_controller() 186 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase) in spi_lock_down() argument 189 struct ich7_spi_regs *ich7_spi = sbase; in spi_lock_down() 193 struct ich9_spi_regs *ich9_spi = sbase; in spi_lock_down() 199 static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase) in spi_lock_status() argument 204 struct ich7_spi_regs *ich7_spi = sbase; in spi_lock_status() [all …]
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/external/mesa3d/src/gallium/drivers/swr/ |
D | swr_context.cpp | 147 size_t zbase, sbase; in swr_transfer_map() local 151 sbase = (z * spr->secondary.qpitch + box->y) * spr->secondary.pitch + in swr_transfer_map() 157 ((uint8_t*)(spr->secondary.xpBaseAddress))[sbase + x]; in swr_transfer_map() 161 ((uint8_t*)(spr->secondary.xpBaseAddress))[sbase + x]; in swr_transfer_map() 164 sbase += spr->secondary.pitch; in swr_transfer_map() 190 size_t zbase, sbase; in swr_transfer_flush_region() local 198 sbase = (z * spr->secondary.qpitch + box.y) * spr->secondary.pitch + in swr_transfer_flush_region() 203 ((uint8_t*)(spr->secondary.xpBaseAddress))[sbase + x] = in swr_transfer_flush_region() 207 ((uint8_t*)(spr->secondary.xpBaseAddress))[sbase + x] = in swr_transfer_flush_region() 211 sbase += spr->secondary.pitch; in swr_transfer_flush_region()
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/external/mesa3d/src/compiler/glsl/ |
D | lower_blend_equation_advanced.cpp | 254 ir_variable *sbase = f->make_temp(glsl_type::float_type, "__blend_sbase"); in set_lum_sat() local 255 f->emit(assign(sbase, satv3(cbase))); in set_lum_sat() 262 f->emit(if_tree(greater(sbase, imm1(0)), in set_lum_sat() 263 assign(color, div(mul(sub(cbase, minbase), ssat), sbase)), in set_lum_sat()
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/external/llvm/lib/Target/AMDGPU/ |
D | VIInstructions.td | 123 (SIload_constant v4i32:$sbase, IMM20bit:$offset), 124 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
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D | VIInstrFormats.td | 93 bits<7> sbase; 97 let Inst{5-0} = sbase{6-1};
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D | SIInstrFormats.td | 246 bits<7> sbase; 249 let Inst{14-9} = sbase{6-1}; 269 bits<7> sbase; 274 let Inst{14-9} = sbase{6-1};
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D | SIInstructions.td | 2368 (smrd_load (SMRDImm i64:$sbase, i32:$offset)), 2369 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset)) 2374 (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), 2375 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset)) 2379 (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), 2380 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset)) 2399 (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), 2400 (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset) 2405 (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)), 2406 (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset) [all …]
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D | SIInstrInfo.td | 1073 let sbase = 0, soff = 0, sdst = sdst_ in { 1094 let sbase = 0; 1106 let sbase = 0; 1115 (ins baseClass:$sbase, smrd_offset:$offset), 1116 opName#" $sdst, $sbase, $offset", [] 1120 (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset), 1121 opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> { 1128 (ins baseClass:$sbase, SReg_32:$soff), 1129 opName#" $sdst, $sbase, $soff", []
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D | SIInstrInfo.cpp | 283 getNamedOperand(LdSt, AMDGPU::OpName::sbase); in getMemOpBaseRegImmOfs() 2199 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase); in legalizeOperandsSMRD()
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/external/deqp/framework/referencerenderer/ |
D | rrFragmentOperations.cpp | 596 const float sbase = saturation(cbase); in setLumSat() local 600 if (sbase > 0.0f) in setLumSat() 601 color = (cbase - minbase) * ssat / sbase; in setLumSat()
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/external/deqp/external/openglcts/modules/common/ |
D | glcBlendEquationAdvancedTests.cpp | 362 float sbase = Saturation(cbase); in SetLumSat() local 365 if (sbase > 0) in SetLumSat() 372 color = (cbase - tcu::Vec4(minbase)) * ssat / sbase; in SetLumSat()
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