| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.cpp | 247 case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false; in ReverseBranchCondition()
248 case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false; in ReverseBranchCondition()
249 case MBlaze::BGT: Cond[0].setImm(MBlaze::BLE); return false; in ReverseBranchCondition()
250 case MBlaze::BGE: Cond[0].setImm(MBlaze::BLT); return false; in ReverseBranchCondition()
251 case MBlaze::BLT: Cond[0].setImm(MBlaze::BGE); return false; in ReverseBranchCondition()
252 case MBlaze::BLE: Cond[0].setImm(MBlaze::BGT); return false; in ReverseBranchCondition()
253 case MBlaze::BEQI: Cond[0].setImm(MBlaze::BNEI); return false; in ReverseBranchCondition()
254 case MBlaze::BNEI: Cond[0].setImm(MBlaze::BEQI); return false; in ReverseBranchCondition()
255 case MBlaze::BGTI: Cond[0].setImm(MBlaze::BLEI); return false; in ReverseBranchCondition()
256 case MBlaze::BGEI: Cond[0].setImm(MBlaze::BLTI); return false; in ReverseBranchCondition()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 101 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
152 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
154 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
157 .setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm()); in mergeIfPossible()
160 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
162 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
165 .setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm()); in mergeIfPossible()
167 RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts); in mergeIfPossible()
|
| D | R600InstrInfo.cpp | 784 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
800 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
949 MO.setImm(OPCODE_IS_NOT_ZERO_INT); in ReverseBranchCondition()
952 MO.setImm(OPCODE_IS_ZERO_INT); in ReverseBranchCondition()
955 MO.setImm(OPCODE_IS_NOT_ZERO); in ReverseBranchCondition()
958 MO.setImm(OPCODE_IS_ZERO); in ReverseBranchCondition()
995 MI.getOperand(8).setImm(0); in PredicateInstruction()
1383 MIB->getOperand(20).setImm(0); in buildSlotOfVectorInstruction()
1416 MI.getOperand(Idx).setImm(Imm); in setImmOperand()
1505 FlagOp.setImm(1); in addFlag()
[all …]
|
| D | R600Packetizer.cpp | 226 MI->getOperand(LastOp).setImm(Bit); in setIsLastBit()
307 MI->getOperand(Op).setImm(BS[i]); in addToPacket()
311 MI.getOperand(Op).setImm(BS.back()); in addToPacket()
|
| D | R600ControlFlowFinalizer.cpp | 449 ClauseHead.getOperand(7).setImm(ClauseContent.size() - 1); in MakeALUClause()
469 Clause.first->getOperand(0).setImm(0); in EmitALUClause()
481 MI.getOperand(0).setImm(Addr + MI.getOperand(0).getImm()); in CounterPropagateAddr()
623 IfOrElseInst->getOperand(1).setImm(1); in runOnMachineFunction()
|
| D | SIShrinkInstructions.cpp | 234 Src.setImm(ReverseImm); in runOnMachineFunction()
261 NextMI.getOperand(0).setImm(Nop0 + Nop1 - 1); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 112 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
163 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
165 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
168 .setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm()); in mergeIfPossible()
171 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
173 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
176 .setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm()); in mergeIfPossible()
178 RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts); in mergeIfPossible()
|
| D | R600InstrInfo.cpp | 774 PredSet->getOperand(2).setImm(Cond[1].getImm()); in insertBranch()
790 PredSet->getOperand(2).setImm(Cond[1].getImm()); in insertBranch()
938 MO.setImm(R600::PRED_SETNE_INT); in reverseBranchCondition()
941 MO.setImm(R600::PRED_SETE_INT); in reverseBranchCondition()
944 MO.setImm(R600::PRED_SETNE); in reverseBranchCondition()
947 MO.setImm(R600::PRED_SETE); in reverseBranchCondition()
977 MI.getOperand(8).setImm(0); in PredicateInstruction()
1362 MIB->getOperand(20).setImm(0); in buildSlotOfVectorInstruction()
1395 MI.getOperand(Idx).setImm(Imm); in setImmOperand()
1480 FlagOp.setImm(1); in addFlag()
[all …]
|
| D | R600Packetizer.cpp | 224 MI->getOperand(LastOp).setImm(Bit); in setIsLastBit()
305 MI->getOperand(Op).setImm(BS[i]); in addToPacket()
309 MI.getOperand(Op).setImm(BS.back()); in addToPacket()
|
| D | SIShrinkInstructions.cpp | 316 Src.setImm(ReverseImm); in runOnMachineFunction()
342 NextMI.getOperand(0).setImm(Nop0 + Nop1 - 1); in runOnMachineFunction()
404 Src.setImm(ReverseImm); in runOnMachineFunction()
|
| D | SIFoldOperands.cpp | 184 Mod.setImm(Mod.getImm() | SISrcMods::OP_SEL_0); in updateOperand()
185 Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1); in updateOperand()
189 Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1); in updateOperand()
842 DefClamp->setImm(1); in tryFoldClamp()
964 DefOMod->setImm(OMod); in tryFoldOMod()
|
| D | R600ControlFlowFinalizer.cpp | 465 ClauseHead.getOperand(7).setImm(ClauseContent.size() - 1); in MakeALUClause()
483 Clause.first->getOperand(0).setImm(0); in EmitALUClause()
494 MI.getOperand(0).setImm(Addr + MI.getOperand(0).getImm()); in CounterPropagateAddr()
638 IfOrElseInst->getOperand(1).setImm(1); in runOnMachineFunction()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinRegisterInfo.cpp | 224 MI.getOperand(FIPos+1).setImm(Offset); in eliminateFrameIndex()
235 MI.getOperand(FIPos+1).setImm(-Offset); in eliminateFrameIndex()
297 MI.getOperand(FIPos+1).setImm(Offset); in eliminateFrameIndex()
309 MI.getOperand(FIPos+1).setImm(Offset); in eliminateFrameIndex()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 74 MI.getOperand(FIOperandNum - 1).setImm(Offset); in eliminateFrameIndex()
95 ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset)); in eliminateFrameIndex()
|
| D | WebAssemblySetP2AlignOperands.cpp | 104 MI.getOperand(3).setImm(P2Align); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 80 MI.getOperand(FIOperandNum - 1).setImm(Offset); in eliminateFrameIndex()
101 ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset)); in eliminateFrameIndex()
|
| D | WebAssemblyCFGStackify.cpp | 269 BlockTops[&MI]->getOperand(0).setImm(int32_t(retType)); in FixEndsAtEndOfFunction()
273 LoopTops[&MI]->getOperand(0).setImm(int32_t(retType)); in FixEndsAtEndOfFunction()
|
| D | WebAssemblySetP2AlignOperands.cpp | 75 MI.getOperand(OperandNo).setImm(P2Align); in RewriteP2Align()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86EvexToVex.cpp | 163 Imm.setImm(Imm.getImm() * Scale); in performCustomAdjustments()
180 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1)); in performCustomAdjustments()
|
| D | X86InstrBuilder.h | 137 MI->getOperand(Operand + 1).setImm(1); in setDirectAddressInInstr()
139 MI->getOperand(Operand + 3).setImm(0); in setDirectAddressInInstr()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 367 MI.getOperand(3).setImm(3 - Immed); in simplifyCode()
458 MI.getOperand(2).setImm(NewElem); in simplifyCode()
1209 BI1->getOperand(0).setImm(NewPredicate1); in eliminateRedundantCompare()
1212 BI2->getOperand(0).setImm(NewPredicate2); in eliminateRedundantCompare()
1215 CMPI1->getOperand(2).setImm(NewImm1); in eliminateRedundantCompare()
1228 CMPI2->getOperand(2).setImm(NewImm2); in eliminateRedundantCompare()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineOperand.h | 424 void setImm(int64_t immVal) { in setImm() function
473 Op.setImm(Val); in CreateImm()
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInst.h | 73 void setImm(int64_t Val) { in setImm() function
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInstrInfo.cpp | 760 Operand.setImm(Operand.getImm() | innerLoopMask); in setInnerLoop()
766 Operand.setImm(Operand.getImm() | memReorderDisabledMask); in setMemReorderDisabled()
773 Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask); in setMemStoreReorderEnabled()
789 Operand.setImm(Operand.getImm() | outerLoopMask); in setOuterLoop()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 158 MI.getOperand(3).setImm(3 - Immed); in simplifyCode()
|