1 //=- WebAssemblySetP2AlignOperands.cpp - Set alignments on loads and stores -=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// This file sets the p2align operands on load and store instructions.
12 ///
13 //===----------------------------------------------------------------------===//
14
15 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
16 #include "WebAssembly.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
19 #include "llvm/CodeGen/MachineMemOperand.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 using namespace llvm;
24
25 #define DEBUG_TYPE "wasm-set-p2align-operands"
26
27 namespace {
28 class WebAssemblySetP2AlignOperands final : public MachineFunctionPass {
29 public:
30 static char ID; // Pass identification, replacement for typeid
WebAssemblySetP2AlignOperands()31 WebAssemblySetP2AlignOperands() : MachineFunctionPass(ID) {}
32
getPassName() const33 StringRef getPassName() const override {
34 return "WebAssembly Set p2align Operands";
35 }
36
getAnalysisUsage(AnalysisUsage & AU) const37 void getAnalysisUsage(AnalysisUsage &AU) const override {
38 AU.setPreservesCFG();
39 AU.addPreserved<MachineBlockFrequencyInfo>();
40 AU.addPreservedID(MachineDominatorsID);
41 MachineFunctionPass::getAnalysisUsage(AU);
42 }
43
44 bool runOnMachineFunction(MachineFunction &MF) override;
45 };
46 } // end anonymous namespace
47
48 char WebAssemblySetP2AlignOperands::ID = 0;
49 INITIALIZE_PASS(WebAssemblySetP2AlignOperands, DEBUG_TYPE,
50 "Set the p2align operands for WebAssembly loads and stores",
51 false, false)
52
createWebAssemblySetP2AlignOperands()53 FunctionPass *llvm::createWebAssemblySetP2AlignOperands() {
54 return new WebAssemblySetP2AlignOperands();
55 }
56
RewriteP2Align(MachineInstr & MI,unsigned OperandNo)57 static void RewriteP2Align(MachineInstr &MI, unsigned OperandNo) {
58 assert(MI.getOperand(OperandNo).getImm() == 0 &&
59 "ISel should set p2align operands to 0");
60 assert(MI.hasOneMemOperand() &&
61 "Load and store instructions have exactly one mem operand");
62 assert((*MI.memoperands_begin())->getSize() ==
63 (UINT64_C(1)
64 << WebAssembly::GetDefaultP2Align(MI.getOpcode())) &&
65 "Default p2align value should be natural");
66 assert(MI.getDesc().OpInfo[OperandNo].OperandType ==
67 WebAssembly::OPERAND_P2ALIGN &&
68 "Load and store instructions should have a p2align operand");
69 uint64_t P2Align = Log2_64((*MI.memoperands_begin())->getAlignment());
70
71 // WebAssembly does not currently support supernatural alignment.
72 P2Align = std::min(
73 P2Align, uint64_t(WebAssembly::GetDefaultP2Align(MI.getOpcode())));
74
75 MI.getOperand(OperandNo).setImm(P2Align);
76 }
77
runOnMachineFunction(MachineFunction & MF)78 bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) {
79 LLVM_DEBUG({
80 dbgs() << "********** Set p2align Operands **********\n"
81 << "********** Function: " << MF.getName() << '\n';
82 });
83
84 bool Changed = false;
85
86 for (auto &MBB : MF) {
87 for (auto &MI : MBB) {
88 switch (MI.getOpcode()) {
89 case WebAssembly::LOAD_I32:
90 case WebAssembly::LOAD_I64:
91 case WebAssembly::LOAD_F32:
92 case WebAssembly::LOAD_F64:
93 case WebAssembly::LOAD8_S_I32:
94 case WebAssembly::LOAD8_U_I32:
95 case WebAssembly::LOAD16_S_I32:
96 case WebAssembly::LOAD16_U_I32:
97 case WebAssembly::LOAD8_S_I64:
98 case WebAssembly::LOAD8_U_I64:
99 case WebAssembly::LOAD16_S_I64:
100 case WebAssembly::LOAD16_U_I64:
101 case WebAssembly::LOAD32_S_I64:
102 case WebAssembly::LOAD32_U_I64:
103 case WebAssembly::ATOMIC_LOAD_I32:
104 case WebAssembly::ATOMIC_LOAD8_U_I32:
105 case WebAssembly::ATOMIC_LOAD16_U_I32:
106 case WebAssembly::ATOMIC_LOAD_I64:
107 case WebAssembly::ATOMIC_LOAD8_U_I64:
108 case WebAssembly::ATOMIC_LOAD16_U_I64:
109 case WebAssembly::ATOMIC_LOAD32_U_I64:
110 case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
111 case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
112 case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
113 case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
114 case WebAssembly::ATOMIC_RMW8_U_AND_I32:
115 case WebAssembly::ATOMIC_RMW8_U_AND_I64:
116 case WebAssembly::ATOMIC_RMW8_U_OR_I32:
117 case WebAssembly::ATOMIC_RMW8_U_OR_I64:
118 case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
119 case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
120 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
121 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
122 case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
123 case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
124 case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
125 case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
126 case WebAssembly::ATOMIC_RMW16_U_AND_I32:
127 case WebAssembly::ATOMIC_RMW16_U_AND_I64:
128 case WebAssembly::ATOMIC_RMW16_U_OR_I32:
129 case WebAssembly::ATOMIC_RMW16_U_OR_I64:
130 case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
131 case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
132 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
133 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
134 case WebAssembly::ATOMIC_RMW_ADD_I32:
135 case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
136 case WebAssembly::ATOMIC_RMW_SUB_I32:
137 case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
138 case WebAssembly::ATOMIC_RMW_AND_I32:
139 case WebAssembly::ATOMIC_RMW32_U_AND_I64:
140 case WebAssembly::ATOMIC_RMW_OR_I32:
141 case WebAssembly::ATOMIC_RMW32_U_OR_I64:
142 case WebAssembly::ATOMIC_RMW_XOR_I32:
143 case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
144 case WebAssembly::ATOMIC_RMW_XCHG_I32:
145 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
146 case WebAssembly::ATOMIC_RMW_ADD_I64:
147 case WebAssembly::ATOMIC_RMW_SUB_I64:
148 case WebAssembly::ATOMIC_RMW_AND_I64:
149 case WebAssembly::ATOMIC_RMW_OR_I64:
150 case WebAssembly::ATOMIC_RMW_XOR_I64:
151 case WebAssembly::ATOMIC_RMW_XCHG_I64:
152 RewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo);
153 break;
154 case WebAssembly::STORE_I32:
155 case WebAssembly::STORE_I64:
156 case WebAssembly::STORE_F32:
157 case WebAssembly::STORE_F64:
158 case WebAssembly::STORE8_I32:
159 case WebAssembly::STORE16_I32:
160 case WebAssembly::STORE8_I64:
161 case WebAssembly::STORE16_I64:
162 case WebAssembly::STORE32_I64:
163 case WebAssembly::ATOMIC_STORE_I32:
164 case WebAssembly::ATOMIC_STORE8_I32:
165 case WebAssembly::ATOMIC_STORE16_I32:
166 case WebAssembly::ATOMIC_STORE_I64:
167 case WebAssembly::ATOMIC_STORE8_I64:
168 case WebAssembly::ATOMIC_STORE16_I64:
169 case WebAssembly::ATOMIC_STORE32_I64:
170 RewriteP2Align(MI, WebAssembly::StoreP2AlignOperandNo);
171 break;
172 default:
173 break;
174 }
175 }
176 }
177
178 return Changed;
179 }
180