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/external/libunwind/src/ia64/
Dgetcontext.S51 st8.spill [r2] = r1, (SC_FLAGS - GR(1)) // M3
66 st8.spill [r2] = r12, (GR(4) - GR(12)) // M3
70 stf.spill [r3] = f2 // M2
71 stf.spill [r8] = f16 // M3
76 stf.spill [r9] = f24, (FR(31) - FR(24)) // M2
80 stf.spill [r9] = f31 // M2
81 st8.spill [r2] = r4, (GR(5) - GR(4)) // M3, bank 1
85 .mem.offset 0,0; st8.spill [r2] = r5, (GR(6) - GR(5)) // M4, bank 0
86 .mem.offset 8,0; st8.spill [r3] = r7, (BR(0) - GR(7)) // M3, bank 0
90 st8.spill [r2] = r6, (BR(1) - GR(6)) // M2, bank 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/AMDGPU/
Dstack-id.mir7 # CHECK: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, stack-id: 0,
8 # CHECK: - { id: 1, type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0,
9 # CHECK: - { id: 2, type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 9,
12 # CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 16,
15 # CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8,
18 # CHECK: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4,
24 - { id: 0, type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 9 }
25 - { id: 1, type: spill-slot, offset: 0, size: 8, alignment: 4, stack-id: 0 }
26 - { id: 2, type: spill-slot, offset: 0, size: 4, alignment: 4 }
28 - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, alignment: 4, stack-id: 3 }
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dspill-offset-calculation.ll10 ; Occupy 4092 bytes of scratch, so the offset of the spill of %a just fits in
19 ; Force %a to spill.
31 ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
43 ; Force %a to spill
55 ; Occupy 4088 bytes of scratch, so that the spill of the last subreg of %a
67 ; Force %a to spill.
74 ; Ensure the spill is of the full super-reg.
83 ; Occupy 4092 bytes of scratch, so that the spill of the last subreg of %a
98 ; Force %a to spill.
105 ; Ensure the spill is of the full super-reg.
[all …]
Dsgpr-spill-wrong-stack-id.mir7 # FI ID used for an SGPR spill to a normal frame index.
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
48 # NOSHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
51 # NOSHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
54 # NOSHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
57 # NOSHARE: - { id: 3, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
Dspill-m0.ll1 ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -mattr=+vgpr-spilling -verify-machineinst…
2 ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mcpu=tonga …
3 ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mattr=+vgpr-spilling -verify-machineinst…
4 ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mcpu=tonga …
5 ; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=1 -march=amdgcn -mcpu=tonga …
62 ; m0 is killed, so it isn't necessary during the entry block spill to preserve it
113 ; Force save and restore of m0 during SMEM spill
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-vector-list-spill.ll3 ; FIXME: We should not generate ld/st for such register spill/fill, because the
5 ; spill/fill algorithm is optimized, this test case may not be triggered. And
7 define i32 @spill.DPairReg(i32* %arg1, i32 %arg2) {
8 ; CHECK-LABEL: spill.DPairReg:
27 define i16 @spill.DTripleReg(i16* %arg1, i32 %arg2) {
28 ; CHECK-LABEL: spill.DTripleReg:
47 define i16 @spill.DQuadReg(i16* %arg1, i32 %arg2) {
48 ; CHECK-LABEL: spill.DQuadReg:
67 define i32 @spill.QPairReg(i32* %arg1, i32 %arg2) {
68 ; CHECK-LABEL: spill.QPairReg:
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-vector-list-spill.ll3 ; FIXME: We should not generate ld/st for such register spill/fill, because the
5 ; spill/fill algorithm is optimized, this test case may not be triggered. And
7 define i32 @spill.DPairReg(i32* %arg1, i32 %arg2) {
8 ; CHECK-LABEL: spill.DPairReg:
27 define i16 @spill.DTripleReg(i16* %arg1, i32 %arg2) {
28 ; CHECK-LABEL: spill.DTripleReg:
47 define i16 @spill.DQuadReg(i16* %arg1, i32 %arg2) {
48 ; CHECK-LABEL: spill.DQuadReg:
67 define i32 @spill.QPairReg(i32* %arg1, i32 %arg2) {
68 ; CHECK-LABEL: spill.QPairReg:
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dpartial-fold64.ll3 define i32 @fold64to32(i64 %add, i32 %spill) {
10 %sub = sub i32 %spill, %trunc
14 define i8 @fold64to8(i64 %add, i8 %spill) {
21 %sub = sub i8 %spill, %trunc
25 ; Do not fold a 4-byte store into a 8-byte spill slot
32 define i32 @nofold(i64 %add, i64 %spill) {
36 %truncspill = trunc i64 %spill to i32
Dpartial-fold32.ll3 define fastcc i8 @fold32to8(i32 %add, i8 %spill) {
10 %sub = sub i8 %spill, %trunc
14 ; Do not fold a 1-byte store into a 4-byte spill slot
15 define fastcc i8 @nofold(i32 %add, i8 %spill) {
23 %sub = sub i8 %spill, %trunc
Dpr27681.mir18 - { id: 0, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '$esi' }
19 - { id: 1, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '$edi' }
20 - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '$ebx' }
21 - { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$ebp' }
23 - { id: 0, type: spill-slot, offset: -53, size: 1, alignment: 1 }
24 - { id: 1, type: spill-slot, offset: -48, size: 4, alignment: 4 }
25 - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
Dsetjmp-spills.ll11 ; Test that llc avoids reusing spill slots in functions that call
20 ; spill slot.
39 ; Again, keep enough variables live that they need spill slots. Since
41 ; compiler should not reuse the spill slots. longjmp() can return to
42 ; where the first spill slots were still live.
/external/libffi/src/ia64/
Dunix.S308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 16
324 st8.spill [r17] = in1, 16
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/ia64/
Dunix.S308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 16
324 st8.spill [r17] = in1, 16
[all …]
/external/llvm/test/CodeGen/X86/
Dpr27681.mir19 - { id: 0, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%esi' }
20 - { id: 1, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%edi' }
21 - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%ebx' }
22 - { id: 3, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%ebp' }
24 - { id: 0, type: spill-slot, offset: -53, size: 1, alignment: 1 }
25 - { id: 1, type: spill-slot, offset: -48, size: 4, alignment: 4 }
26 - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
Dsetjmp-spills.ll11 ; Test that llc avoids reusing spill slots in functions that call
20 ; spill slot.
39 ; Again, keep enough variables live that they need spill slots. Since
41 ; compiler should not reuse the spill slots. longjmp() can return to
42 ; where the first spill slots were still live.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/XCore/
Depilogue_prologue.ll8 ; FP + small frame: spill FP+SR = entsp 2
29 ; FP + small frame: spill FP+SR+R0+LR = entsp 3 + extsp 1
45 ; !FP + small frame: spill R0+LR = entsp 2
62 ; FP + large frame: spill FP+SR = entsp 2 + 100000
78 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
94 ; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1
139 ; !FP + large frame: spill SR+SR+R4+LR = entsp 4 + 200000
187 ; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1
201 ; !FP + large frame: spill SR+SR+LR = entsp 3 + 256
215 ; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
[all …]
Dllvm-intrinsics.ll154 ; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
155 ; But we dont actually spill or restore R0:1
176 ; !FP: spill R0:1+R4:10 = entsp 2+7
177 ; But we dont actually spill or restore R0:1
201 ; FP: spill FP+SR+R0:1+R4:9+LR = entsp 2+2+6 + extsp 1
202 ; But we dont actually spill or restore R0:1
226 ; !FP: spill R0:1+R4:10+LR = entsp 2+7+1
227 ; But we dont actually spill or restore R0:1
252 ; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
253 ; We dont spill R0:1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dframe-21.ll1 ; Test the allocation of emergency spill slots.
5 ; For frames of size less than 4096 - 2*160, no emercengy spill slot
18 ; spill slots. Check the minimum such case.
30 ; in reach, so the maximum frame size without emergency spill slots is
32 ; case where we still need no emergency spill slots ...
55 ; Check the maximum case where we still need no emergency spill slots ...
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/micromips-sizereduction/
Dmicromips-lwp-swp.mir51 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
54 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
57 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
119 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
122 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
125 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
187 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
190 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
193 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
255 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
[all …]
Dmicromips-no-lwp-swp.mir49 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
52 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
108 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
111 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
167 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
170 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
226 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
229 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dframeindex.ll21 %2 = alloca [492 x i8] ; Push the frame--acounting for the emergency spill
37 %2 = alloca [497 x i8] ; Push the frame--acounting for the emergency spill
55 %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
75 %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
128 %2 = alloca [1004 x i8] ; Push the frame--acounting for the emergency spill
144 %2 = alloca [1009 x i8] ; Push the frame--acounting for the emergency spill
162 %2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
182 %2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
235 %2 = alloca [2028 x i8] ; Push the frame--acounting for the emergency spill
251 %2 = alloca [2033 x i8] ; Push the frame--acounting for the emergency spill
[all …]
/external/llvm/test/CodeGen/XCore/
Depilogue_prologue.ll8 ; FP + small frame: spill FP+SR = entsp 2
29 ; FP + small frame: spill FP+SR+R0+LR = entsp 3 + extsp 1
45 ; !FP + small frame: spill R0+LR = entsp 2
62 ; FP + large frame: spill FP+SR = entsp 2 + 100000
83 ; !FP + large frame: spill SR+SR = entsp 2 + 100000
102 ; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1
155 ; !FP + large frame: spill SR+SR+R4+LR = entsp 4 + 200000
209 ; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1
223 ; !FP + large frame: spill SR+SR+LR = entsp 3 + 256
237 ; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
[all …]
Dllvm-intrinsics.ll154 ; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
155 ; But we dont actually spill or restore R0:1
176 ; !FP: spill R0:1+R4:10 = entsp 2+7
177 ; But we dont actually spill or restore R0:1
201 ; FP: spill FP+SR+R0:1+R4:9+LR = entsp 2+2+6 + extsp 1
202 ; But we dont actually spill or restore R0:1
226 ; !FP: spill R0:1+R4:10+LR = entsp 2+7+1
227 ; But we dont actually spill or restore R0:1
252 ; FP: spill FP+SR+R0:1+R4:9 = entsp 2+2+6
253 ; We dont spill R0:1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Coroutines/
Dcoro-spill-after-phi.ll41 ; CHECK: %phi2.spill.addr = getelementptr inbounds %f.Frame, %f.Frame* %FramePtr, i32 0, i32 5
42 ; CHECK: store i32 %phi2, i32* %phi2.spill.addr
43 ; CHECK: %phi1.spill.addr = getelementptr inbounds %f.Frame, %f.Frame* %FramePtr, i32 0, i32 4
44 ; CHECK: store i32 %phi1, i32* %phi1.spill.addr
/external/llvm/test/CodeGen/MIR/Mips/
Dmemory-operands.mir40 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
72 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
74 - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4,
76 - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4,

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