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Searched refs:v128i8 (Results 1 – 25 of 33) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td89 CCIfType<[v32i32,v64i16,v128i8],
95 CCIfType<[v32i32,v64i16,v128i8],
100 CCIfType<[v32i32,v64i16,v128i8],
106 CCIfType<[v32i32,v64i16,v128i8],
121 CCIfType<[v32i32,v64i16,v128i8],
126 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsicsV60.td53 def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))),
54 (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
62 def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))),
63 (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
DHexagonRegisterInfo.td276 [v64i8, v128i8, v64i8]>;
283 [v128i8, v256i8, v128i8]>;
DHexagonISelLoweringHVX.cpp18 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
19 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
29 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
45 addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
62 MVT ByteV = Use64b ? MVT::v64i8 : MVT::v128i8; in initializeHVXLowering()
63 MVT ByteW = Use64b ? MVT::v128i8 : MVT::v256i8; in initializeHVXLowering()
DHexagonISelDAGToDAG.cpp112 case MVT::v128i8: in SelectIndexedLoad()
504 case MVT::v128i8: in SelectIndexedStore()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-128b.ll9 %t0 = call <128 x i8> @llvm.ctpop.v128i8(<128 x i8> %a0)
38 %t0 = call <128 x i8> @llvm.ctlz.v128i8(<128 x i8> %a0)
74 %t0 = call <128 x i8> @llvm.cttz.v128i8(<128 x i8> %a0)
112 declare <128 x i8> @llvm.ctpop.v128i8(<128 x i8>) #0
116 declare <128 x i8> @llvm.ctlz.v128i8(<128 x i8>) #0
120 declare <128 x i8> @llvm.cttz.v128i8(<128 x i8>) #0
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h75 v128i8 = 28, //128 x i8 enumerator
272 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
332 case v128i8: in getVectorElementType()
378 case v128i8: in getVectorNumElements()
504 case v128i8: in getSizeInBits()
610 if (NumElements == 128) return MVT::v128i8; in getVectorVT()
DValueTypes.td52 def v128i8 : ValueType<1024,28>; //128 x i8 vector value
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h78 v128i8 = 31, //128 x i8 enumerator
376 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
443 case v128i8: in getVectorElementType()
526 case v128i8: in getVectorNumElements()
740 case v128i8: in getSizeInBits()
851 if (NumElements == 128) return MVT::v128i8; in getVectorVT()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp204 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) { in CC_Hexagon_VarArg()
349 LocVT == MVT::v128i8)) { in CC_HexagonVector()
372 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { in CC_HexagonVector()
418 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || in RetCC_Hexagon()
546 ty == MVT::v128i8 || in IsHvxVectorType()
899 VT == MVT::v64i16 || VT == MVT::v128i8); in getIndexedAddressParts()
1126 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { in LowerFormalArguments()
1134 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { in LowerFormalArguments()
1759 addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering()
1765 addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering()
[all …]
DHexagonRegisterInfo.td230 [v128i8, v64i16, v32i32, v16i64], 1024,
234 [v128i8, v64i16, v32i32, v16i64], 1024,
DHexagonIntrinsicsV60.td134 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
135 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
154 def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
155 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
DHexagonISelDAGToDAG.cpp285 case MVT::v128i8: in SelectIndexedLoad()
573 case MVT::v128i8: in SelectIndexedStore()
DHexagonInstrInfoV60.td798 defm : STrivv_pats <v128i8, v256i8>;
848 defm : vS32b_ai_pats <v64i8, v128i8>;
873 defm : LDrivv_pats <v128i8, v256i8>;
913 defm : vL32b_ai_pats <v64i8, v128i8>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp157 case MVT::v128i8: return "v128i8"; in getEVTString()
238 case MVT::v128i8: return VectorType::get(Type::getInt8Ty(Context), 128); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp160 case MVT::v128i8: return "v128i8"; in getEVTString()
238 case MVT::v128i8: return VectorType::get(Type::getInt8Ty(Context), 128); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dv60-halide-vcombinei8.ll3 ; do not crash with Cannot select on vcombine on v128i8
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td54 def v128i8 : ValueType<1024,31>; //128 x i8 vector value
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp88 case MVT::v128i8: return "MVT::v128i8"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenTarget.cpp96 case MVT::v128i8: return "MVT::v128i8"; in getEnumName()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvector-reduce-and.ll1006 %1 = call i8 @llvm.experimental.vector.reduce.and.i8.v128i8(<128 x i8> %a0)
1028 declare i8 @llvm.experimental.vector.reduce.and.i8.v128i8(<128 x i8>)
Dvector-reduce-or.ll1006 %1 = call i8 @llvm.experimental.vector.reduce.or.i8.v128i8(<128 x i8> %a0)
1028 declare i8 @llvm.experimental.vector.reduce.or.i8.v128i8(<128 x i8>)
Dvector-reduce-xor.ll1006 %1 = call i8 @llvm.experimental.vector.reduce.xor.i8.v128i8(<128 x i8> %a0)
1028 declare i8 @llvm.experimental.vector.reduce.xor.i8.v128i8(<128 x i8>)
Dvector-reduce-add.ll1118 %1 = call i8 @llvm.experimental.vector.reduce.add.i8.v128i8(<128 x i8> %a0)
1140 declare i8 @llvm.experimental.vector.reduce.add.i8.v128i8(<128 x i8>)
/external/llvm/include/llvm/IR/
DIntrinsics.td185 def llvm_v128i8_ty : LLVMType<v128i8>; //128 x i8

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