Home
last modified time | relevance | path

Searched refs:v16i32 (Results 1 – 25 of 107) sorted by relevance

12345

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td88 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
93 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
97 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
102 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
103 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
104 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
105 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
106 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
108 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
113 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
[all …]
DX86TargetTransformInfo.cpp312 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
313 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
314 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
315 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
472 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
473 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
474 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
485 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) in getArithmeticInstrCost()
903 { TTI::SK_Broadcast, MVT::v16i32, 1 }, // vpbroadcastd in getShuffleCost()
908 { TTI::SK_Reverse, MVT::v16i32, 1 }, // vpermd in getShuffleCost()
[all …]
DX86CallingConv.td121 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
151 CCIfType<[v16i32, v8i64, v16f32, v8f64], CCAssignToStack<64, 64>>
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
303 CCIfType<[v16f32, v8f64, v16i32, v8i64],
550 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
570 CCIfType<[v16i32, v8i64, v16f32, v8f64],
613 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
673 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
731 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-64b.ll25 %t0 = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %a0)
52 %t0 = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a0)
108 %t0 = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %a0)
115 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) #0
119 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>) #0
123 declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>) #0
Dbswap.ll17 %v0 = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %a0)
40 declare <16 x i32> @llvm.bswap.v16i32(<16 x i32>) #0
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
558 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost()
559 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost()
564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
567 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
568 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost()
[all …]
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
366 CCIfType<[v16i32, v8i64, v16f32, v8f64],
406 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daarch64-minmaxv.ll145 declare i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32>)
154 %r = call i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32> %arr.load)
169 declare i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32>)
178 %r = call i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32> %arr.load)
193 declare i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32>)
202 %r = call i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32> %arr.load)
217 declare i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32>)
226 %r = call i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32> %arr.load)
Daarch64-addv.ll61 declare i32 @llvm.experimental.vector.reduce.add.i32.v16i32(<16 x i32>)
67 %r = call i32 @llvm.experimental.vector.reduce.add.i32.v16i32(<16 x i32> %bin.rdx)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h91 v16i32 = 42, // 16 x i32 enumerator
266 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
346 case v16i32: in getVectorElementType()
392 case v16i32: in getVectorNumElements()
499 case v16i32: in getSizeInBits()
628 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dscatter-schedule.ll19 …call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %x270, <16 x i32*> %x335, i32 4, <16 x i…
22 declare void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> , <16 x i32*> , i32, <16 x i1> )
Davx512vpopcntdq-intrinsics.ll23 %1 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %b)
41 %1 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %a)
87 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>)
Davx512cd-intrinsics.ll58 %1 = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a, i1 false)
61 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1) #0
87 %1 = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a, i1 false)
Davx512-masked-memop-64-32.ll12 …%res = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask,…
23 …%res = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask,…
35 …call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%m…
85 declare <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
86 declare void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
Dbitcast-setcc-512.ll78 define i16 @v16i32(<16 x i32> %a, <16 x i32> %b) {
79 ; SSE-LABEL: v16i32:
92 ; AVX1-LABEL: v16i32:
110 ; AVX2-LABEL: v16i32:
123 ; AVX512F-LABEL: v16i32:
131 ; AVX512BW-LABEL: v16i32:
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td86 CCIfType<[v16i32,v32i16,v64i8],
92 CCIfType<[v16i32,v32i16,v64i8],
118 CCIfType<[v16i32,v32i16,v64i8],
DHexagonIntrinsicsV60.td16 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
17 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
19 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
20 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
29 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
30 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
38 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
39 (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
68 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1),
73 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/X86/
Dgather_scatter.ll31 ; AVX512-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 …
46 ; AVX512-NEXT: [[WIDE_MASKED_LOAD_1:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<1…
61 ; AVX512-NEXT: [[WIDE_MASKED_LOAD_2:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<1…
76 ; AVX512-NEXT: [[WIDE_MASKED_LOAD_3:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<1…
164 ; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(…
172 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_1:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
180 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_2:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
188 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_3:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
196 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_4:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
204 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_5:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h94 v16i32 = 45, // 16 x i32 enumerator
370 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
469 case v16i32: in getVectorElementType()
545 case v16i32: in getVectorNumElements()
730 case v16i32: in getSizeInBits()
869 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
85 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
105 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
167 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
173 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td114 …CCIfType<[i64, f64, v2i32, v2f32, v4i32, v4f32, v8i32, v8f32, v16i32, v16f32, v2i64, v2f64, v4i16,…
119 CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>
131 …CCIfType<[i64, f64, v2i32, v2f32, v4i32, v4f32, v8i32, v8f32, v16i32, v16f32, v2i64, v2f64, v4i16,…
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp121 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
122 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
125 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
150 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
151 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dv6vec_zero.ll5 ; generating a v16i32 constant pool node.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp182 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
183 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
186 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
211 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
212 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
212 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
448 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()

12345