Home
last modified time | relevance | path

Searched refs:v1i64 (Results 1 – 25 of 176) sorted by relevance

12345678

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dmachine-copy-prop.ll41 …call void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64> <i64 4096>, <1 x i64> <i64 -1>, i64 0, i…
42 …%vld2_lane = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> <i64 11…
45 …%vld2_lane1 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> %vld2_…
49 …call void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64> %vld2_lane1.0.extract, <1 x i64> %vld2_lane1…
55 %sqadd1 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 -1>, <1 x i64> <i64 1>)
56 …%sqadd2 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> %vset_lane603, <1 x i64> %sqadd…
57 %sqadd3 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 1>, <1 x i64> %sqadd2)
61 %vpadal = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %sext.i)
89 declare void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i8* nocapture)
91 declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i…
[all …]
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
8 ; scalarization will cause an assertion failure, as v1i64 is a legal type in
66 ; the i64 out of the v1i64 operand, and truncate that scalar instead.
Daarch64-neon-v1i1-setcc.ll4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
Darm64-neon-vector-list-spill.ll142 …tail call void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroini…
153 …tail call void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroini…
164 …tail call void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroini…
173 declare void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64>, <1 x i64>, i64, i64*)
174 declare void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64, i64*)
175 declare void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i64…
/external/llvm/test/CodeGen/AArch64/
Dmachine-copy-prop.ll41 …call void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64> <i64 4096>, <1 x i64> <i64 -1>, i64 0, i…
42 …%vld2_lane = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> <i64 11…
45 …%vld2_lane1 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> %vld2_…
49 …call void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64> %vld2_lane1.0.extract, <1 x i64> %vld2_lane1…
55 %sqadd1 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 -1>, <1 x i64> <i64 1>)
56 …%sqadd2 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> %vset_lane603, <1 x i64> %sqadd…
57 %sqadd3 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 1>, <1 x i64> %sqadd2)
61 %vpadal = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %sext.i)
89 declare void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i8* nocapture)
91 declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i…
[all …]
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
8 ; scalarization will cause an assertion failure, as v1i64 is a legal type in
66 ; the i64 out of the v1i64 operand, and truncate that scalar instead.
Daarch64-neon-v1i1-setcc.ll4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
Darm64-neon-vector-list-spill.ll142 …tail call void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroini…
153 …tail call void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroini…
164 …tail call void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroini…
173 declare void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64>, <1 x i64>, i64, i64*)
174 declare void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64, i64*)
175 declare void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i64…
Darm64-extract_subvector.ll29 define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
30 ; CHECK-LABEL: v1i64:
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCallingConv.td31 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
49 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
63 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
75 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
91 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
138 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
148 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
163 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
175 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
/external/clang/test/CodeGen/
Dconst-init.c137 typedef long long v1i64 __attribute((vector_size(8))); in g28()
143 static v1i64 a = (v1i64)10LL; in g28()
Dsystemz-abi-vector.c23 typedef __attribute__((vector_size(8))) long long v1i64; typedef
94 v1i64 pass_v1i64(v1i64 arg) { return arg; } in pass_v1i64()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h66 v1i64 = 24, // 1 x i64 enumerator
202 case v1i64: in getVectorElementType()
238 case v1i64: return 1; in getVectorNumElements()
266 case v1i64: in getSizeInBits()
357 if (NumElements == 1) return MVT::v1i64; in getVectorVT()
432 case 1: return MVT::v1i64; in getIntVectorWithNumElements()
489 V == MVT::v1i64 || V==MVT::v2f32); in is64BitVector()
/external/llvm/test/CodeGen/ARM/
Dneon_vshl_minint.ll9 …%vshl.i = tail call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> undef, <1 x i64> <i64 -922337…
13 declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dneon_vshl_minint.ll9 …%vshl.i = tail call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> undef, <1 x i64> <i64 -922337…
13 declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>)
Darm-vlddup.ll35 declare %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8*, i32)
40 declare %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8*, i32)
45 declare %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0i8(i8*, i32)
79 %tmp = tail call %struct.uint64x1x2_t @llvm.arm.neon.vld2dup.v1i64.p0i8(i8* %src, i32 8)
111 %tmp = tail call %struct.uint64x1x3_t @llvm.arm.neon.vld3dup.v1i64.p0i8(i8* %src, i32 8)
143 %tmp = tail call %struct.uint64x1x4_t @llvm.arm.neon.vld4dup.v1i64.p0i8(i8* %src, i32 8)
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenDAGISel.inc1251 /* 2543*/ OPC_CheckChild1Type, MVT::v1i64,
1260 …// Src: (st FPR64:{ *:[v1i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ …
1261 …// Dst: (STRDroW FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wexte…
1267 …// Src: (st FPR64:{ *:[v1i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ …
1268 …// Dst: (STRDroX FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xexte…
1286 …// Src: (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed7s32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, simm7s4…
1287 …:[i32] } FPR64:{ *:[v1i64] }:$Rt, ssub:{ *:[i32] }), (CPYi32:{ *:[i32] } (SUBREG_TO_REG:{ *:[f128]…
1293 …// Src: (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:…
1294 … // Dst: (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
1950 /* 3979*/ OPC_CheckChild0Type, MVT::v1i64,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
58 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
91 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
107 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
163 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
179 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
204 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
225 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
/external/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
58 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
91 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
107 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
163 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
179 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
203 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
224 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h95 v1i64 = 45, // 1 x i64 enumerator
242 SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 || in is64BitVector()
349 case v1i64: in getVectorElementType()
422 case v1i64: in getVectorNumElements()
474 case v1i64: in getSizeInBits()
633 if (NumElements == 1) return MVT::v1i64; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2973 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3000 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3027 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3054 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3081 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3108 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3135 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3162 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3189 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3209 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2762 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2789 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2816 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2843 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2870 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2897 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2924 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2951 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2978 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
2998 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dmmx-arg-passing.ll8 ; On Darwin x86-32, v1i64 values are passed in memory. In this example, they
11 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvpadal.ll26 %tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
53 %tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
113 declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
117 declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
/external/llvm/test/CodeGen/X86/
Dmmx-arg-passing.ll6 ; On Darwin x86-32, v1i64 values are passed in memory. In this example, they
9 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.

12345678