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Searched refs:v4i64 (Results 1 – 25 of 142) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
159 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
160 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
200 { ISD::SHL, MVT::v4i64, 2 }, in getArithmeticInstrCost()
201 { ISD::SRL, MVT::v4i64, 4 }, in getArithmeticInstrCost()
202 { ISD::SRA, MVT::v4i64, 4 }, in getArithmeticInstrCost()
221 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. in getArithmeticInstrCost()
227 { ISD::SDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
231 { ISD::UDIV, MVT::v4i64, 4*20 }, in getArithmeticInstrCost()
253 { ISD::SHL, MVT::v4i64, 2 }, // psllq. in getArithmeticInstrCost()
[all …]
DX86CallingConv.td62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
340 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
362 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
403 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
445 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
520 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
536 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
555 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
420 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
421 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
422 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
424 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
425 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
430 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp309 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
330 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
435 { ISD::MUL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
480 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
514 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
515 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
557 { ISD::SHL, MVT::v4i64, 2+2 }, in getArithmeticInstrCost()
558 { ISD::SRL, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
559 { ISD::SRA, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
571 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td54 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
55 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
56 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
57 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
58 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
59 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
64 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
69 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
74 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
79 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
[all …]
DX86CallingConv.td116 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
147 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
299 CCIfType<[v8f32, v4f64, v8i32, v4i64],
544 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
566 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
610 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
669 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
727 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td315 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
318 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)))),
598 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
606 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
2224 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2226 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2228 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2230 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2314 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2316 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/MemorySanitizer/
Dmasked-store-load.ll8 declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)
13 …tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
26 ; CHECK: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %[[A]], <4 x i64>* %[[D]], i32 1, <4 …
42 ; CHECK: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i…
58 ; ADDR: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1…
77 ; CHECK: %[[E:.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* %[[D]], i32 1, <4 x …
103 …tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask)
111 ; CHECK: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> zeroinitializer, <4 x i64>* %[[D]], i…
112 ; CHECK: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i…
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h68 v4i64 = 26, // 4 x i64 enumerator
204 case v4i64: in getVectorElementType()
229 case v4i64: in getVectorNumElements()
281 case v4i64: in getSizeInBits()
359 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
505 V == MVT::v16i16 || V == MVT::v8i32 || V == MVT::v4i64); in is256BitVector()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h97 v4i64 = 47, // 4 x i64 enumerator
259 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
351 case v4i64: in getVectorElementType()
407 case v4i64: in getVectorNumElements()
493 case v4i64: in getSizeInBits()
635 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/X86/
Dbswap.ll15 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
38 …nd an estimated cost of 14 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
42 …und an estimated cost of 2 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
46 …und an estimated cost of 4 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
50 …und an estimated cost of 1 for instruction: %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
53 %bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h100 v4i64 = 50, // 4 x i64 enumerator
363 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64); in is256BitVector()
480 case v4i64: in getVectorElementType()
574 case v4i64: in getVectorNumElements()
718 case v4i64: in getSizeInBits()
876 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
449 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Dbswap.ll20 declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>);
45 %r2 = tail call <4 x i64> @llvm.bswap.v4i64(<4 x i64> <i64 272, i64 272, i64 272, i64 272>)
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll11 define <4 x i64> @v4i64-cmp(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
39 define <4 x i64> @v4i64-cmpeq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
Dfold-vector-sext-crash.ll6 ; due to an illegal build_vector of type MVT::v4i64.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dbitcast-setcc-256.ll210 define i4 @v4i64(<4 x i64> %a, <4 x i64> %b) {
211 ; SSE2-SSSE3-LABEL: v4i64:
239 ; AVX1-LABEL: v4i64:
251 ; AVX2-LABEL: v4i64:
259 ; AVX512F-LABEL: v4i64:
267 ; AVX512BW-LABEL: v4i64:
Dbitcast-and-setcc-256.ll9 define i4 @v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i64> %d) {
10 ; SSE2-SSSE3-LABEL: v4i64:
60 ; AVX1-LABEL: v4i64:
78 ; AVX2-LABEL: v4i64:
92 ; AVX512F-LABEL: v4i64:
101 ; AVX512BW-LABEL: v4i64:
Dfold-vector-sext-crash.ll7 ; due to an illegal build_vector of type MVT::v4i64.
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1309 …dd:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPADDQYrr:{ *:[v4i64]…
1320 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPADDQZ256rr:{ *:[v4i6…
1897 …ub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPSUBQYrr:{ *:[v4i64]…
1908 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPSUBQZ256rr:{ *:[v4i6…
2377 … *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMULLQZ256rr:{ *:[v4i6…
3622 …and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPANDYrr:{ *:[v4i64]…
3633 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPANDQZ256rr:{ *:[v4i6…
3644 …nd:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VANDPSYrr:{ *:[v4i64]…
4700 …(or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPORYrr:{ *:[v4i64] …
4711 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPORQZ256rr:{ *:[v4i64…
[all …]
/external/llvm/test/Analysis/CostModel/X86/
Dctbits-cost.ll15 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>)
34 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %a)
99 declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1)
127 %ctlz = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 0)
136 %ctlz = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 1)
255 declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1)
283 %cttz = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 0)
292 %cttz = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 1)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp295 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
300 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
301 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
302 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
303 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
603 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll15 @v4i64 = global <4 x i32*>* zeroinitializer, align 8
61 define void @store.v4i64.0001(<4 x i32*> %arg) sanitize_address {
62 ; ALL-LABEL: @store.v4i64.0001
63 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
189 define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) sanitize_address {
190 ; ALL-LABEL: @load.v4i64.0001
191 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp134 case MVT::v4i64: return "v4i64"; in getEVTString()
181 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4); in getTypeForEVT()
/external/llvm/test/CodeGen/AMDGPU/
Dctpop64.ll6 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
78 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
110 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone

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