Home
last modified time | relevance | path

Searched refs:v4i8 (Results 1 – 25 of 118) sorted by relevance

12345

/external/clang/test/CodeGen/
Dbuiltins-mips.c10 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef
19 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; in foo()
27 v4i8_a = (v4i8) {1, 2, 3, 0xFF}; in foo()
28 v4i8_b = (v4i8) {2, 4, 6, 8}; in foo()
91 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
124 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; in foo()
142 v4i8_a = (v4i8) {1, 2, 3, 4}; in foo()
145 v4i8_a = (v4i8) {128, 64, 32, 16}; in foo()
168 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; in foo()
211 v4i8_b = (v4i8) {1, 2, 3, 4}; in foo()
[all …]
Dsystemz-abi-vector.c15 typedef __attribute__((vector_size(4))) char v4i8; typedef
50 v4i8 pass_v4i8(v4i8 arg) { return arg; } in pass_v4i8()
143 struct agg_v4i8 { v4i8 a; };
166 struct agg_novector1 { v4i8 a; v4i8 b; };
171 struct agg_novector2 { v4i8 a; float b; };
176 struct agg_novector3 { v4i8 a; int : 0; };
181 struct agg_novector4 { v4i8 a __attribute__((aligned (8))); };
253 v4i8 va_v4i8(__builtin_va_list l) { return __builtin_va_arg(l, v4i8); } in va_v4i8()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dneon-truncStore-extLoad.ll23 define void @truncStore.v4i8(<4 x i32> %a, <4 x i8>* %result) {
24 ; CHECK-LABEL: truncStore.v4i8:
44 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
45 ; CHECK-LABEL: loadSExt.v4i8:
52 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
53 ; CHECK-LABEL: loadZExt.v4i8:
/external/llvm/test/CodeGen/AArch64/
Dneon-truncStore-extLoad.ll34 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
35 ; CHECK-LABEL: loadSExt.v4i8:
42 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
43 ; CHECK-LABEL: loadZExt.v4i8:
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td17 def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
39 defm : bitconvert_32<v4i8, i32>;
89 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
253 // Adds two v4i8: Hexagon does not have an insn for this one, so we
255 def: Pat<(v4i8 (add (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
258 // Subtract two v4i8: Hexagon does not have an insn for this one, so we
260 def: Pat<(v4i8 (sub (v4i8 IntRegs:$Rs), (v4i8 IntRegs:$Rt))),
266 def: Pat<(v4i8 (select I1:$Pu, V4I8:$Rs, V4I8:$Rt)),
328 def: Pat<(v4i8 (trunc V4I16:$Rs)),
391 // Multiplies two v4i8 vectors.
[all …]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp589 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, in getCastInstrCost()
621 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
622 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
634 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, in getCastInstrCost()
652 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, in getCastInstrCost()
653 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, in getCastInstrCost()
668 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, in getCastInstrCost()
676 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
677 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
689 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, in getCastInstrCost()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1329 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1331 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1333 def : BitconvertPat<f32, v4i8, FGR32, DSPR>;
1335 def : BitconvertPat<v4i8, f32, DSPR, FGR32>;
1339 def : DSPPat<(v4i8 (load addr:$a)),
1340 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1343 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1357 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1358 def : DSPBinPat<ADDU_QB, v4i8, add>;
1359 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc901 …// (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{…
1250 …// (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{…
2800 …// (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4…
2822 …// (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4…
3271 …// (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:…
3280 …// (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:…
4286 …/ (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$i…
4349 … (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$im…
4365 …:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{…
4413 …[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpn…
[all …]
DMipsGenDAGISel.inc557 /* 917*/ OPC_CheckChild1Type, MVT::v4i8,
569 …// Src: (st DSPR:{ *:[v4i8] }:$val, addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predica…
570 …// Dst: (SW (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$val, GPR32:{ *:[i32] }), addr:{ *:[iP…
1338 /* 2388*/ /*SwitchType*/ 25, MVT::v4i8,// ->2415
1346 MVT::v4i8, 2/*#Ops*/, 4, 5,
1347 …// Src: (ld:{ *:[v4i8] } addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - …
1348 … // Dst: (COPY_TO_REGCLASS:{ *:[v4i8] } (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a), DSPR:{ *:[i32] })
7667 …trinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$r…
7668 … // Dst: (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7674 …trinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$r…
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h70 v4i8 = 23, // 4 x i8 enumerator
234 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || in is32BitVector()
327 case v4i8: in getVectorElementType()
404 case v4i8: in getVectorNumElements()
462 case v4i8: in getSizeInBits()
605 if (NumElements == 4) return MVT::v4i8; in getVectorVT()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1318 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1320 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1324 def : DSPPat<(v4i8 (load addr:$a)),
1325 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1328 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1342 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1343 def : DSPBinPat<ADDU_QB, v4i8, add>;
1344 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1345 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1362 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td16 CCIfType<[i32,v2i16,v4i8],
40 CCIfType<[i32,v2i16,v4i8],
68 CCIfType<[i32,v2i16,v4i8],
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h55 v4i8 = 13, // 4 x i8 enumerator
191 case v4i8 : in getVectorElementType()
226 case v4i8: in getVectorNumElements()
258 case v4i8: in getSizeInBits()
340 if (NumElements == 4) return MVT::v4i8; in getVectorVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1217 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, in getCastInstrCost()
1253 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
1254 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
1266 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, in getCastInstrCost()
1284 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, in getCastInstrCost()
1285 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, in getCastInstrCost()
1300 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, in getCastInstrCost()
1308 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
1309 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, in getCastInstrCost()
1321 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, in getCastInstrCost()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dpr35443.ll19 …%wide.masked.load66 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* bitcast (i8* getelemen…
30 declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32, <4 x i1>, <4 x i8>)
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h73 v4i8 = 26, // 4 x i8 enumerator
337 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
438 case v4i8: in getVectorElementType()
571 case v4i8: in getVectorNumElements()
666 case v4i8: in getSizeInBits()
846 if (NumElements == 4) return MVT::v4i8; in getVectorVT()
/external/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll13 ; v4i8
54 ; v4i8
104 ; v4i8 x v4i16
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll13 ; v4i8
54 ; v4i8
104 ; v4i8 x v4i16
/external/llvm/test/CodeGen/SystemZ/
Dvec-const-01.ll73 ; Test an all-zeros v4i8 that gets promoted to v16i8.
81 ; Test a mixed v4i8 that gets promoted to v16i8 (mask 0x9000).
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-const-01.ll73 ; Test an all-zeros v4i8 that gets promoted to v16i8.
81 ; Test a mixed v4i8 that gets promoted to v16i8 (mask 0x9000).
/external/llvm/test/CodeGen/X86/
D2011-12-8-bitcastintprom.ll3 ; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1848 "llvm.nvvm.suld.1d.v4i8.clamp">;
1893 "llvm.nvvm.suld.1d.array.v4i8.clamp">;
1938 "llvm.nvvm.suld.2d.v4i8.clamp">;
1983 "llvm.nvvm.suld.2d.array.v4i8.clamp">;
2028 "llvm.nvvm.suld.3d.v4i8.clamp">;
2074 "llvm.nvvm.suld.1d.v4i8.trap">;
2119 "llvm.nvvm.suld.1d.array.v4i8.trap">;
2164 "llvm.nvvm.suld.2d.v4i8.trap">;
2209 "llvm.nvvm.suld.2d.array.v4i8.trap">;
2254 "llvm.nvvm.suld.3d.v4i8.trap">;
[all …]
/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp121 case MVT::v4i8: return "v4i8"; in getEVTString()
168 case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4); in getTypeForEVT()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
275 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1874 "llvm.nvvm.suld.1d.v4i8.clamp">;
1919 "llvm.nvvm.suld.1d.array.v4i8.clamp">;
1964 "llvm.nvvm.suld.2d.v4i8.clamp">;
2009 "llvm.nvvm.suld.2d.array.v4i8.clamp">;
2054 "llvm.nvvm.suld.3d.v4i8.clamp">;
2100 "llvm.nvvm.suld.1d.v4i8.trap">;
2145 "llvm.nvvm.suld.1d.array.v4i8.trap">;
2190 "llvm.nvvm.suld.2d.v4i8.trap">;
2235 "llvm.nvvm.suld.2d.array.v4i8.trap">;
2280 "llvm.nvvm.suld.3d.v4i8.trap">;
[all …]

12345