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1 // REQUIRES: mips-registered-target
2 // RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \
3 // RUN:   | FileCheck %s
4 
5 typedef int q31;
6 typedef int i32;
7 typedef unsigned int ui32;
8 typedef long long a64;
9 
10 typedef signed char v4i8 __attribute__ ((vector_size(4)));
11 typedef signed char v4q7 __attribute__ ((vector_size(4)));
12 typedef short v2i16 __attribute__ ((vector_size(4)));
13 typedef short v2q15 __attribute__ ((vector_size(4)));
14 
foo()15 void foo() {
16   v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c;
17   v2i16 v2i16_r, v2i16_a, v2i16_b, v2i16_c;
18   v4q7 v4q7_r, v4q7_a, v4q7_b;
19   v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c;
20   q31 q31_r, q31_a, q31_b, q31_c;
21   i32 i32_r, i32_a, i32_b, i32_c;
22   ui32 ui32_r, ui32_a, ui32_b, ui32_c;
23   a64 a64_r, a64_a, a64_b;
24 
25   // MIPS DSP Rev 1
26 
27   v4i8_a = (v4i8) {1, 2, 3, 0xFF};
28   v4i8_b = (v4i8) {2, 4, 6, 8};
29   v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b);
30 // CHECK: call <4 x i8> @llvm.mips.addu.qb
31   v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b);
32 // CHECK: call <4 x i8> @llvm.mips.addu.s.qb
33   v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b);
34 // CHECK: call <4 x i8> @llvm.mips.subu.qb
35   v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b);
36 // CHECK: call <4 x i8> @llvm.mips.subu.s.qb
37 
38   v2q15_a = (v2q15) {0x0000, 0x8000};
39   v2q15_b = (v2q15) {0x8000, 0x8000};
40   v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b);
41 // CHECK: call <2 x i16> @llvm.mips.addq.ph
42   v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b);
43 // CHECK: call <2 x i16> @llvm.mips.addq.s.ph
44   v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b);
45 // CHECK: call <2 x i16> @llvm.mips.subq.ph
46   v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b);
47 // CHECK: call <2 x i16> @llvm.mips.subq.s.ph
48 
49   a64_a = 0x12345678;
50   i32_b = 0x80000000;
51   i32_c = 0x11112222;
52   a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c);
53 // CHECK: call i64 @llvm.mips.madd
54   a64_a = 0x12345678;
55   ui32_b = 0x80000000;
56   ui32_c = 0x11112222;
57   a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c);
58 // CHECK: call i64 @llvm.mips.maddu
59   a64_a = 0x12345678;
60   i32_b = 0x80000000;
61   i32_c = 0x11112222;
62   a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c);
63 // CHECK: call i64 @llvm.mips.msub
64   a64_a = 0x12345678;
65   ui32_b = 0x80000000;
66   ui32_c = 0x11112222;
67   a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c);
68 // CHECK: call i64 @llvm.mips.msubu
69 
70   q31_a = 0x12345678;
71   q31_b = 0x7FFFFFFF;
72   q31_r = __builtin_mips_addq_s_w(q31_a, q31_b);
73 // CHECK: call i32 @llvm.mips.addq.s.w
74   q31_r = __builtin_mips_subq_s_w(q31_a, q31_b);
75 // CHECK: call i32 @llvm.mips.subq.s.w
76 
77   i32_a = 0xFFFFFFFF;
78   i32_b = 1;
79   i32_r = __builtin_mips_addsc(i32_a, i32_b);
80 // CHECK: call i32 @llvm.mips.addsc
81   i32_a = 0;
82   i32_b = 1;
83   i32_r = __builtin_mips_addwc(i32_a, i32_b);
84 // CHECK: call i32 @llvm.mips.addwc
85 
86   i32_a = 20;
87   i32_b = 0x1402;
88   i32_r = __builtin_mips_modsub(i32_a, i32_b);
89 // CHECK: call i32 @llvm.mips.modsub
90 
91   v4i8_a = (v4i8) {1, 2, 3, 4};
92   i32_r = __builtin_mips_raddu_w_qb(v4i8_a);
93 // CHECK: call i32 @llvm.mips.raddu.w.qb
94 
95   v2q15_a = (v2q15) {0xFFFF, 0x8000};
96   v2q15_r = __builtin_mips_absq_s_ph(v2q15_a);
97 // CHECK: call <2 x i16> @llvm.mips.absq.s.ph
98   q31_a = 0x80000000;
99   q31_r = __builtin_mips_absq_s_w(q31_a);
100 // CHECK: call i32 @llvm.mips.absq.s.w
101 
102   v2q15_a = (v2q15) {0x1234, 0x5678};
103   v2q15_b = (v2q15) {0x1111, 0x2222};
104   v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b);
105 // CHECK: call <4 x i8> @llvm.mips.precrq.qb.ph
106 
107   v2q15_a = (v2q15) {0x7F79, 0xFFFF};
108   v2q15_b = (v2q15) {0x7F81, 0x2000};
109   v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b);
110 // CHECK: call <4 x i8> @llvm.mips.precrqu.s.qb.ph
111   q31_a = 0x12345678;
112   q31_b = 0x11112222;
113   v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b);
114 // CHECK: call <2 x i16> @llvm.mips.precrq.ph.w
115   q31_a = 0x7000FFFF;
116   q31_b = 0x80000000;
117   v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b);
118 // CHECK: call <2 x i16> @llvm.mips.precrq.rs.ph.w
119   v2q15_a = (v2q15) {0x1234, 0x5678};
120   q31_r = __builtin_mips_preceq_w_phl(v2q15_a);
121 // CHECK: call i32 @llvm.mips.preceq.w.phl
122   q31_r = __builtin_mips_preceq_w_phr(v2q15_a);
123 // CHECK: call i32 @llvm.mips.preceq.w.phr
124   v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
125   v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a);
126 // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbl
127   v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a);
128 // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbr
129   v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a);
130 // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbla
131   v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a);
132 // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbra
133   v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a);
134 // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbl
135   v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a);
136 // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbr
137   v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a);
138 // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbla
139   v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a);
140 // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbra
141 
142   v4i8_a = (v4i8) {1, 2, 3, 4};
143   v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2);
144 // CHECK: call <4 x i8> @llvm.mips.shll.qb
145   v4i8_a = (v4i8) {128, 64, 32, 16};
146   v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2);
147 // CHECK: call <4 x i8> @llvm.mips.shrl.qb
148   v2q15_a = (v2q15) {0x0001, 0x8000};
149   v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2);
150 // CHECK: call <2 x i16> @llvm.mips.shll.ph
151   v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2);
152 // CHECK: call <2 x i16> @llvm.mips.shll.s.ph
153   v2q15_a = (v2q15) {0x7FFF, 0x8000};
154   v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2);
155 // CHECK: call <2 x i16> @llvm.mips.shra.ph
156   v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2);
157 // CHECK: call <2 x i16> @llvm.mips.shra.r.ph
158   q31_a = 0x70000000;
159   q31_r = __builtin_mips_shll_s_w(q31_a, 2);
160 // CHECK: call i32 @llvm.mips.shll.s.w
161   q31_a = 0x7FFFFFFF;
162   q31_r = __builtin_mips_shra_r_w(q31_a, 2);
163 // CHECK: call i32 @llvm.mips.shra.r.w
164   a64_a = 0x1234567887654321LL;
165   a64_r = __builtin_mips_shilo(a64_a, -8);
166 // CHECK: call i64 @llvm.mips.shilo
167 
168   v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7};
169   v2q15_b = (v2q15) {0x1234, 0x5678};
170   v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b);
171 // CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbl
172   v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b);
173 // CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbr
174   v2q15_a = (v2q15) {0x7FFF, 0x8000};
175   v2q15_b = (v2q15) {0x7FFF, 0x8000};
176   v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b);
177 // CHECK: call <2 x i16> @llvm.mips.mulq.rs.ph
178   v2q15_a = (v2q15) {0x1234, 0x8000};
179   v2q15_b = (v2q15) {0x5678, 0x8000};
180   q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b);
181 // CHECK: call i32 @llvm.mips.muleq.s.w.phl
182   q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b);
183 // CHECK: call i32 @llvm.mips.muleq.s.w.phr
184   a64_a = 0;
185   v2q15_a = (v2q15) {0x0001, 0x8000};
186   v2q15_b = (v2q15) {0x0002, 0x8000};
187   a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
188 // CHECK: call i64 @llvm.mips.mulsaq.s.w.ph
189   a64_a = 0;
190   v2q15_b = (v2q15) {0x0001, 0x8000};
191   v2q15_c = (v2q15) {0x0002, 0x8000};
192   a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c);
193 // CHECK: call i64 @llvm.mips.maq.s.w.phl
194   a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c);
195 // CHECK: call i64 @llvm.mips.maq.s.w.phr
196   a64_a = 0x7FFFFFF0;
197   a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c);
198 // CHECK: call i64 @llvm.mips.maq.sa.w.phl
199   a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c);
200 // CHECK: call i64 @llvm.mips.maq.sa.w.phr
201   i32_a = 0x80000000;
202   i32_b = 0x11112222;
203   a64_r = __builtin_mips_mult(i32_a, i32_b);
204 // CHECK: call i64 @llvm.mips.mult
205   ui32_a = 0x80000000;
206   ui32_b = 0x11112222;
207   a64_r = __builtin_mips_multu(ui32_a, ui32_b);
208 // CHECK: call i64 @llvm.mips.multu
209 
210   a64_a = 0;
211   v4i8_b = (v4i8) {1, 2, 3, 4};
212   v4i8_c = (v4i8) {4, 5, 6, 7};
213   a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c);
214 // CHECK: call i64 @llvm.mips.dpau.h.qbl
215   a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c);
216 // CHECK: call i64 @llvm.mips.dpau.h.qbr
217   a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c);
218 // CHECK: call i64 @llvm.mips.dpsu.h.qbl
219   a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c);
220 // CHECK: call i64 @llvm.mips.dpsu.h.qbr
221   a64_a = 0;
222   v2q15_b = (v2q15) {0x0001, 0x8000};
223   v2q15_c = (v2q15) {0x0002, 0x8000};
224   a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
225 // CHECK: call i64 @llvm.mips.dpaq.s.w.ph
226   a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c);
227 // CHECK: call i64 @llvm.mips.dpsq.s.w.ph
228   a64_a = 0;
229   q31_b = 0x80000000;
230   q31_c = 0x80000000;
231   a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c);
232 // CHECK: call i64 @llvm.mips.dpaq.sa.l.w
233   a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c);
234 // CHECK: call i64 @llvm.mips.dpsq.sa.l.w
235 
236   v4i8_a = (v4i8) {1, 4, 10, 8};
237   v4i8_b = (v4i8) {1, 2, 100, 8};
238   __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
239 // CHECK: call void @llvm.mips.cmpu.eq.qb
240   __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b);
241 // CHECK: call void @llvm.mips.cmpu.lt.qb
242   __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b);
243 // CHECK: call void @llvm.mips.cmpu.le.qb
244   i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b);
245 // CHECK: call i32 @llvm.mips.cmpgu.eq.qb
246   i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b);
247 // CHECK: call i32 @llvm.mips.cmpgu.lt.qb
248   i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b);
249 // CHECK: call i32 @llvm.mips.cmpgu.le.qb
250   v2q15_a = (v2q15) {0x1111, 0x1234};
251   v2q15_b = (v2q15) {0x4444, 0x1234};
252   __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
253 // CHECK: call void @llvm.mips.cmp.eq.ph
254   __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b);
255 // CHECK: call void @llvm.mips.cmp.lt.ph
256   __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b);
257 // CHECK: call void @llvm.mips.cmp.le.ph
258 
259   a64_a = 0xFFFFF81230000000LL;
260   i32_r = __builtin_mips_extr_s_h(a64_a, 4);
261 // CHECK: call i32 @llvm.mips.extr.s.h
262   a64_a = 0x8123456712345678LL;
263   i32_r = __builtin_mips_extr_w(a64_a, 31);
264 // CHECK: call i32 @llvm.mips.extr.w
265   i32_r = __builtin_mips_extr_rs_w(a64_a, 31);
266 // CHECK: call i32 @llvm.mips.extr.rs.w
267   i32_r = __builtin_mips_extr_r_w(a64_a, 31);
268 // CHECK: call i32 @llvm.mips.extr.r.w
269   a64_a = 0x1234567887654321LL;
270   i32_r = __builtin_mips_extp(a64_a, 3);
271 // CHECK: call i32 @llvm.mips.extp
272   a64_a = 0x123456789ABCDEF0LL;
273   i32_r = __builtin_mips_extpdp(a64_a, 7);
274 // CHECK: call i32 @llvm.mips.extpdp
275 
276   __builtin_mips_wrdsp(2052, 3);
277 // CHECK: call void @llvm.mips.wrdsp
278   i32_r = __builtin_mips_rddsp(3);
279 // CHECK: call i32 @llvm.mips.rddsp
280   i32_a = 0xFFFFFFFF;
281   i32_b = 0x12345678;
282   __builtin_mips_wrdsp((16<<7) + 4, 3);
283 // CHECK: call void @llvm.mips.wrdsp
284   i32_r = __builtin_mips_insv(i32_a, i32_b);
285 // CHECK: call i32 @llvm.mips.insv
286   i32_a = 0x1234;
287   i32_r = __builtin_mips_bitrev(i32_a);
288 // CHECK: call i32 @llvm.mips.bitrev
289   v2q15_a = (v2q15) {0x1111, 0x2222};
290   v2q15_b = (v2q15) {0x3333, 0x4444};
291   v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b);
292 // CHECK: call <2 x i16> @llvm.mips.packrl.ph
293   i32_a = 100;
294   v4i8_r = __builtin_mips_repl_qb(i32_a);
295 // CHECK: call <4 x i8> @llvm.mips.repl.qb
296   i32_a = 0x1234;
297   v2q15_r = __builtin_mips_repl_ph(i32_a);
298 // CHECK: call <2 x i16> @llvm.mips.repl.ph
299   v4i8_a = (v4i8) {1, 4, 10, 8};
300   v4i8_b = (v4i8) {1, 2, 100, 8};
301   __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
302 // CHECK: call void @llvm.mips.cmpu.eq.qb
303   v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b);
304 // CHECK: call <4 x i8> @llvm.mips.pick.qb
305   v2q15_a = (v2q15) {0x1111, 0x1234};
306   v2q15_b = (v2q15) {0x4444, 0x1234};
307   __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
308 // CHECK: call void @llvm.mips.cmp.eq.ph
309   v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b);
310 // CHECK: call <2 x i16> @llvm.mips.pick.ph
311   a64_a = 0x1234567887654321LL;
312   i32_b = 0x11112222;
313   __builtin_mips_wrdsp(0, 1);
314 // CHECK: call void @llvm.mips.wrdsp
315   a64_r = __builtin_mips_mthlip(a64_a, i32_b);
316 // CHECK: call i64 @llvm.mips.mthlip
317   i32_r = __builtin_mips_bposge32();
318 // CHECK: call i32 @llvm.mips.bposge32
319   char array_a[100];
320   i32_r = __builtin_mips_lbux(array_a, 20);
321 // CHECK: call i32 @llvm.mips.lbux
322   short array_b[100];
323   i32_r = __builtin_mips_lhx(array_b, 20);
324 // CHECK: call i32 @llvm.mips.lhx
325   int array_c[100];
326   i32_r = __builtin_mips_lwx(array_c, 20);
327 // CHECK: call i32 @llvm.mips.lwx
328 
329   // MIPS DSP Rev 2
330 
331   v4q7_a = (v4q7) {0x81, 0xff, 0x80, 0x23};
332   v4q7_r = __builtin_mips_absq_s_qb (v4q7_a);
333 // CHECK: call <4 x i8> @llvm.mips.absq.s.qb
334 
335   v2q15_a = (v2q15) {0x3334, 0x4444};
336   v2q15_b = (v2q15) {0x1111, 0x2222};
337   v2q15_r = __builtin_mips_addqh_ph(v2q15_a, v2q15_b);
338 // CHECK: call <2 x i16> @llvm.mips.addqh.ph
339   v2q15_a = (v2q15) {0x3334, 0x4444};
340   v2q15_b = (v2q15) {0x1111, 0x2222};
341   v2q15_r = __builtin_mips_addqh_r_ph(v2q15_a, v2q15_b);
342 // CHECK: call <2 x i16> @llvm.mips.addqh.r.ph
343   q31_a = 0x11111112;
344   q31_b = 0x99999999;
345   q31_r = __builtin_mips_addqh_w(q31_a, q31_b);
346 // CHECK: call i32 @llvm.mips.addqh.w
347   q31_a = 0x11111112;
348   q31_b = 0x99999999;
349   q31_r = __builtin_mips_addqh_r_w(q31_a, q31_b);
350 // CHECK: call i32 @llvm.mips.addqh.r.w
351 
352   v2i16_a = (v2i16) {0xffff, 0x2468};
353   v2i16_b = (v2i16) {0x1234, 0x1111};
354   v2i16_r = __builtin_mips_addu_ph(v2i16_a, v2i16_b);
355 // CHECK: call <2 x i16> @llvm.mips.addu.ph
356   v2i16_a = (v2i16) {0xffff, 0x2468};
357   v2i16_b = (v2i16) {0x1234, 0x1111};
358   v2i16_r = __builtin_mips_addu_s_ph(v2i16_a, v2i16_b);
359 // CHECK: call <2 x i16> @llvm.mips.addu.s.ph
360   v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
361   v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
362   v4i8_r = __builtin_mips_adduh_qb(v4i8_a, v4i8_b);
363 // CHECK: call <4 x i8> @llvm.mips.adduh.qb
364   v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
365   v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
366   v4i8_r = __builtin_mips_adduh_r_qb(v4i8_a, v4i8_b);
367 // CHECK: call <4 x i8> @llvm.mips.adduh.r.qb
368 
369   i32_a = 0x12345678;
370   i32_b = 0x87654321;
371   i32_r = __builtin_mips_append(i32_a, i32_b, 16);
372 // CHECK: call i32 @llvm.mips.append
373   i32_a = 0x12345678;
374   i32_b = 0x87654321;
375   i32_r = __builtin_mips_balign(i32_a, i32_b, 3);
376 // CHECK: call i32 @llvm.mips.balign
377 
378   v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
379   v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
380   i32_r = __builtin_mips_cmpgdu_eq_qb(v4i8_a, v4i8_b);
381 // CHECK: call i32 @llvm.mips.cmpgdu.eq.qb
382   v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
383   v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
384   i32_r = __builtin_mips_cmpgdu_lt_qb(v4i8_a, v4i8_b);
385 // CHECK: call i32 @llvm.mips.cmpgdu.lt.qb
386   v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x54};
387   v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
388   i32_r = __builtin_mips_cmpgdu_le_qb(v4i8_a, v4i8_b);
389 // CHECK: call i32 @llvm.mips.cmpgdu.le.qb
390 
391   a64_a = 0x12345678;
392   v2i16_b = (v2i16) {0xffff, 0x1555};
393   v2i16_c = (v2i16) {0x1234, 0x3322};
394   a64_r = __builtin_mips_dpa_w_ph(a64_a, v2i16_b, v2i16_c);
395 // CHECK: call i64 @llvm.mips.dpa.w.ph
396   a64_a = 0x12345678;
397   v2i16_b = (v2i16) {0xffff, 0x1555};
398   v2i16_c = (v2i16) {0x1234, 0x3322};
399   a64_r = __builtin_mips_dps_w_ph(a64_a, v2i16_b, v2i16_c);
400 // CHECK: call i64 @llvm.mips.dps.w.ph
401 
402   a64_a = 0x70000000;
403   v2q15_b = (v2q15) {0x4000, 0x2000};
404   v2q15_c = (v2q15) {0x2000, 0x4000};
405   a64_r = __builtin_mips_dpaqx_s_w_ph(a64_a, v2q15_b, v2q15_c);
406 // CHECK: call i64 @llvm.mips.dpaqx.s.w.ph
407   a64_a = 0x70000000;
408   v2q15_b = (v2q15) {0x4000, 0x2000};
409   v2q15_c = (v2q15) {0x2000, 0x4000};
410   a64_r = __builtin_mips_dpaqx_sa_w_ph(a64_a, v2q15_b, v2q15_c);
411 // CHECK: call i64 @llvm.mips.dpaqx.sa.w.ph
412   a64_a = 0x1111222212345678LL;
413   v2i16_b = (v2i16) {0x1, 0x2};
414   v2i16_c = (v2i16) {0x3, 0x4};
415   a64_r = __builtin_mips_dpax_w_ph(a64_a, v2i16_b, v2i16_c);
416 // CHECK: call i64 @llvm.mips.dpax.w.ph
417   a64_a = 0x9999111112345678LL;
418   v2i16_b = (v2i16) {0x1, 0x2};
419   v2i16_c = (v2i16) {0x3, 0x4};
420   a64_r = __builtin_mips_dpsx_w_ph(a64_a, v2i16_b, v2i16_c);
421 // CHECK: call i64 @llvm.mips.dpsx.w.ph
422   a64_a = 0x70000000;
423   v2q15_b = (v2q15) {0x4000, 0x2000};
424   v2q15_c = (v2q15) {0x2000, 0x4000};
425   a64_r = __builtin_mips_dpsqx_s_w_ph(a64_a, v2q15_b, v2q15_c);
426 // CHECK: call i64 @llvm.mips.dpsqx.s.w.ph
427   a64_a = 0xFFFFFFFF80000000LL;
428   v2q15_b = (v2q15) {0x4000, 0x2000};
429   v2q15_c = (v2q15) {0x2000, 0x4000};
430   a64_r = __builtin_mips_dpsqx_sa_w_ph(a64_a, v2q15_b, v2q15_c);
431 // CHECK: call i64 @llvm.mips.dpsqx.sa.w.ph
432 
433   v2i16_a = (v2i16) {0xffff, 0x2468};
434   v2i16_b = (v2i16) {0x1234, 0x1111};
435   v2i16_r = __builtin_mips_mul_ph(v2i16_a, v2i16_b);
436 // CHECK: call <2 x i16> @llvm.mips.mul.ph
437   v2i16_a = (v2i16) {0x8000, 0x7fff};
438   v2i16_b = (v2i16) {0x1234, 0x1111};
439   v2i16_r = __builtin_mips_mul_s_ph(v2i16_a, v2i16_b);
440 // CHECK: call <2 x i16> @llvm.mips.mul.s.ph
441 
442   q31_a = 0x80000000;
443   q31_b = 0x80000000;
444   q31_r = __builtin_mips_mulq_rs_w(q31_a, q31_b);
445 // CHECK: call i32 @llvm.mips.mulq.rs.w
446   v2q15_a = (v2q15) {0xffff, 0x8000};
447   v2q15_b = (v2q15) {0x1111, 0x8000};
448   v2q15_r = __builtin_mips_mulq_s_ph(v2q15_a, v2q15_b);
449 // CHECK: call <2 x i16> @llvm.mips.mulq.s.ph
450   q31_a = 0x00000002;
451   q31_b = 0x80000000;
452   q31_r = __builtin_mips_mulq_s_w(q31_a, q31_b);
453 // CHECK: call i32 @llvm.mips.mulq.s.w
454   a64_a = 0x19848419;
455   v2i16_b = (v2i16) {0xffff, 0x8000};
456   v2i16_c = (v2i16) {0x1111, 0x8000};
457   a64_r = __builtin_mips_mulsa_w_ph(a64_a, v2i16_b, v2i16_c);
458 // CHECK: call i64 @llvm.mips.mulsa.w.ph
459 
460   v2i16_a = (v2i16) {0x1234, 0x5678};
461   v2i16_b = (v2i16) {0x2233, 0x5566};
462   v4i8_r = __builtin_mips_precr_qb_ph(v2i16_a, v2i16_b);
463 // CHECK: call <4 x i8> @llvm.mips.precr.qb.ph
464   i32_a = 0x12345678;
465   i32_b = 0x33334444;
466   v2i16_r = __builtin_mips_precr_sra_ph_w(i32_a, i32_b, 4);
467 // CHECK: call <2 x i16> @llvm.mips.precr.sra.ph.w
468   i32_a = 0x12345678;
469   i32_b = 0x33334444;
470   v2i16_r = __builtin_mips_precr_sra_r_ph_w(i32_a, i32_b, 4);
471 // CHECK: call <2 x i16> @llvm.mips.precr.sra.r.ph.w
472 
473   i32_a = 0x12345678;
474   i32_b = 0x87654321;
475   i32_r = __builtin_mips_prepend(i32_a, i32_b, 16);
476 // CHECK: call i32 @llvm.mips.prepend
477 
478   v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
479   v4i8_r = __builtin_mips_shra_qb(v4i8_a, 1);
480 // CHECK: call <4 x i8> @llvm.mips.shra.qb
481   v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
482   i32_b = 1;
483   v4i8_r = __builtin_mips_shra_qb(v4i8_a, i32_b);
484 // CHECK: call <4 x i8> @llvm.mips.shra.qb
485   v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
486   v4i8_r = __builtin_mips_shra_r_qb(v4i8_a, 1);
487 // CHECK: call <4 x i8> @llvm.mips.shra.r.qb
488   v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
489   i32_b = 1;
490   v4i8_r = __builtin_mips_shra_r_qb(v4i8_a, i32_b);
491 // CHECK: call <4 x i8> @llvm.mips.shra.r.qb
492   v2i16_a = (v2i16) {0x1357, 0x2468};
493   v2i16_r = __builtin_mips_shrl_ph(v2i16_a, 4);
494 // CHECK: call <2 x i16> @llvm.mips.shrl.ph
495   v2i16_a = (v2i16) {0x1357, 0x2468};
496   i32_b = 8;
497   v2i16_r = __builtin_mips_shrl_ph (v2i16_a, i32_b);
498 // CHECK: call <2 x i16> @llvm.mips.shrl.ph
499 
500   v2q15_a = (v2q15) {0x3334, 0x4444};
501   v2q15_b = (v2q15) {0x1111, 0x2222};
502   v2q15_r = __builtin_mips_subqh_ph(v2q15_a, v2q15_b);
503 // CHECK: call <2 x i16> @llvm.mips.subqh.ph
504   v2q15_a = (v2q15) {0x3334, 0x4444};
505   v2q15_b = (v2q15) {0x1111, 0x2222};
506   v2q15_r = __builtin_mips_subqh_r_ph(v2q15_a, v2q15_b);
507 // CHECK: call <2 x i16> @llvm.mips.subqh.r.ph
508   q31_a = 0x11111112;
509   q31_b = 0x99999999;
510   q31_r = __builtin_mips_subqh_w(q31_a, q31_b);
511 // CHECK: call i32 @llvm.mips.subqh.w
512   q31_a = 0x11111112;
513   q31_b = 0x99999999;
514   q31_r = __builtin_mips_subqh_r_w(q31_a, q31_b);
515 // CHECK: call i32 @llvm.mips.subqh.r.w
516 
517   v2i16_a = (v2i16) {0x1357, 0x4455};
518   v2i16_b = (v2i16) {0x3333, 0x4444};
519   v2i16_r = __builtin_mips_subu_ph(v2i16_a, v2i16_b);
520 // CHECK: call <2 x i16> @llvm.mips.subu.ph
521   v2i16_a = (v2i16) {0x1357, 0x4455};
522   v2i16_b = (v2i16) {0x3333, 0x4444};
523   v2i16_r = __builtin_mips_subu_s_ph(v2i16_a, v2i16_b);
524 // CHECK: call <2 x i16> @llvm.mips.subu.s.ph
525 
526   v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
527   v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
528   v4i8_r = __builtin_mips_subuh_qb(v4i8_a, v4i8_b);
529 // CHECK: call <4 x i8> @llvm.mips.subuh.qb
530   v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
531   v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
532   v4i8_r = __builtin_mips_subuh_r_qb(v4i8_a, v4i8_b);
533 // CHECK: call <4 x i8> @llvm.mips.subuh.r.qb
534 }
535 
test_eh_return_data_regno()536 void test_eh_return_data_regno()
537 {
538   volatile int res;
539   res = __builtin_eh_return_data_regno(0);  // CHECK: store volatile i32 4
540   res = __builtin_eh_return_data_regno(1);  // CHECK: store volatile i32 5
541 }
542