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Searched refs:writeb (Results 1 – 25 of 108) sorted by relevance

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/external/u-boot/board/astro/mcf5373l/
Dfpga.c37 writeb(tmp_char, &gpiop->par_timer); in altera_pre_fn()
45 writeb(0x00, &gpiop->par_pwm); in altera_pre_fn()
47 writeb(0x01, &gpiop->pddr_timer); in altera_pre_fn()
48 writeb(0x25, &gpiop->pddr_qspi); in altera_pre_fn()
49 writeb(0x0c, &gpiop->pddr_uart); in altera_pre_fn()
50 writeb(0x04, &gpiop->pddr_pwm); in altera_pre_fn()
53 writeb(0x08, &gpiop->ppd_uart); in altera_pre_fn()
54 writeb(0x38, &gpiop->ppd_qspi); in altera_pre_fn()
57 writeb(0xFB, &gpiop->pclrr_uart); in altera_pre_fn()
59 writeb(0xFE, &gpiop->pclrr_timer); in altera_pre_fn()
[all …]
Dmcf5373l.c110 writeb(UART_UCR_RESET_RX, &uart->ucr); in rs_serial_init()
111 writeb(UART_UCR_RESET_TX, &uart->ucr); in rs_serial_init()
112 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in rs_serial_init()
113 writeb(UART_UCR_RESET_MR, &uart->ucr); in rs_serial_init()
116 writeb(0, &uart->uimr); in rs_serial_init()
119 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); in rs_serial_init()
121 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); in rs_serial_init()
122 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); in rs_serial_init()
129 writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); in rs_serial_init()
131 writeb((u8) (counter & 0x00ff), &uart->ubg2); in rs_serial_init()
[all …]
/external/u-boot/board/logicpd/omap3som/
Domap3logic.c117 writeb(0x70, GPMC_NAND_COMMAND_0); in spl_board_prepare_for_linux()
118 writeb(-1, GPMC_NAND_DATA_0); in spl_board_prepare_for_linux()
119 writeb(0x7a, GPMC_NAND_COMMAND_0); in spl_board_prepare_for_linux()
120 writeb(0x00, GPMC_NAND_ADDRESS_0); in spl_board_prepare_for_linux()
121 writeb(0x00, GPMC_NAND_ADDRESS_0); in spl_board_prepare_for_linux()
122 writeb(0x00, GPMC_NAND_ADDRESS_0); in spl_board_prepare_for_linux()
123 writeb(-1, GPMC_NAND_COMMAND_0); in spl_board_prepare_for_linux()
126 writeb(NAND_CMD_UNLOCK1, 0x6e00007c); in spl_board_prepare_for_linux()
127 writeb(0x00, GPMC_NAND_ADDRESS_0); in spl_board_prepare_for_linux()
128 writeb(0x00, GPMC_NAND_ADDRESS_0); in spl_board_prepare_for_linux()
[all …]
/external/u-boot/drivers/ata/
Dsata_sil3114.c63 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
65 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
67 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
119 writeb (cmd, port[num].ioaddr.command_addr); in sata_identify()
185 writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr); in set_Feature_cmd()
186 writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr); in set_Feature_cmd()
187 writeb (0, port[num].ioaddr.lbal_addr); in set_Feature_cmd()
188 writeb (0, port[num].ioaddr.lbam_addr); in set_Feature_cmd()
189 writeb (0, port[num].ioaddr.lbah_addr); in set_Feature_cmd()
191 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); in set_Feature_cmd()
[all …]
/external/u-boot/drivers/serial/
Dmcfuart.c34 writeb(UART_UCR_RESET_RX, &uart->ucr); in mcf_serial_init_common()
35 writeb(UART_UCR_RESET_TX, &uart->ucr); in mcf_serial_init_common()
36 writeb(UART_UCR_RESET_ERROR, &uart->ucr); in mcf_serial_init_common()
37 writeb(UART_UCR_RESET_MR, &uart->ucr); in mcf_serial_init_common()
40 writeb(0, &uart->uimr); in mcf_serial_init_common()
43 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); in mcf_serial_init_common()
45 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); in mcf_serial_init_common()
46 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); in mcf_serial_init_common()
53 writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1); in mcf_serial_init_common()
55 writeb((u8)(counter & 0x00ff), &uart->ubg2); in mcf_serial_init_common()
[all …]
Dserial_arc.c44 writeb(arc_console_baud & 0xff, &regs->baudl); in arc_serial_setbrg()
45 writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh); in arc_serial_setbrg()
58 writeb(c, &regs->data); in arc_serial_putc()
142 writeb(arc_console_baud & 0xff, &regs->baudl); in _debug_uart_init()
143 writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh); in _debug_uart_init()
153 writeb(c, &regs->data); in _debug_uart_putc()
/external/u-boot/drivers/usb/musb/
Dmusb_hcd.c421 writeb(hub, &musbr->tar[ep].txhubaddr); in config_hub_port()
422 writeb((chid + 1), &musbr->tar[ep].txhubport); in config_hub_port()
423 writeb(hub, &musbr->tar[ep].rxhubaddr); in config_hub_port()
424 writeb((chid + 1), &musbr->tar[ep].rxhubport); in config_hub_port()
436 writeb(power | MUSB_POWER_RESET, &musbr->power); in musb_port_reset()
441 writeb(power & ~MUSB_POWER_RESET, &musbr->power); in musb_port_reset()
768 writeb(MUSB_CONTROL_EP, &musbr->index); in submit_control_msg()
773 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); in submit_control_msg()
774 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); in submit_control_msg()
782 writeb(devspeed << 6, &musbr->txtype); in submit_control_msg()
[all …]
Dmusb_core.c29 writeb(0, &musbr->intrusbe); in musb_start()
30 writeb(0, &musbr->testmode); in musb_start()
33 writeb(MUSB_POWER_HSENAB, &musbr->power); in musb_start()
42 writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl); in musb_start()
51 writeb(idx, &musbr->dir##fifosz); \
77 writeb(epinfo->epnum, &musbr->index); in musb_configure_ep()
123 writeb(ep, &musbr->index); in write_fifo()
127 writeb(*data++, &musbr->fifox[ep]); in write_fifo()
148 writeb(ep, &musbr->index); in read_fifo()
/external/u-boot/drivers/i2c/
Dfsl_i2c.c183 writeb(dfsr, &base->dfsrr); /* set default filter */ in set_i2c_bus_speed()
184 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
194 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
227 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr); in fsl_i2c_fixup()
237 writeb(0, &base->cr); in fsl_i2c_fixup()
239 writeb(I2C_CR_MSTA | flags, &base->cr); in fsl_i2c_fixup()
240 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr); in fsl_i2c_fixup()
253 writeb(I2C_CR_MEN | flags, &base->cr); in fsl_i2c_fixup()
254 writeb(0, &base->sr); in fsl_i2c_fixup()
273 writeb(0, &base->cr); /* stop I2C controller */ in __i2c_init()
[all …]
Dsh_i2c.c112 writeb(iccl & 0xff, &dev->iccl); in sh_i2c_set_addr()
113 writeb(icch & 0xff, &dev->icch); in sh_i2c_set_addr()
120 writeb(icic, &dev->icic); in sh_i2c_set_addr()
122 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); in sh_i2c_set_addr()
126 writeb(chip << 1, &dev->icdr); in sh_i2c_set_addr()
130 writeb(addr, &dev->icdr); in sh_i2c_set_addr()
132 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr); in sh_i2c_set_addr()
141 writeb(0, &dev->icsr); in sh_i2c_finish()
153 writeb(val, &dev->icdr); in sh_i2c_raw_write()
157 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr); in sh_i2c_raw_write()
[all …]
Dmxc_i2c.c181 writeb(idx, base + (IFDR << reg_shift)); in bus_i2c_set_bus_speed()
184 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); in bus_i2c_set_bus_speed()
185 writeb(0, base + (I2SR << reg_shift)); in bus_i2c_set_bus_speed()
205 writeb(sr | I2SR_IAL, base + in wait_for_sr_state()
208 writeb(sr & ~I2SR_IAL, base + in wait_for_sr_state()
234 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); in tx_byte()
235 writeb(byte, base + (I2DR << reg_shift)); in tx_byte()
266 writeb(temp, base + (I2CR << reg_shift)); in i2c_imx_stop()
295 writeb(I2CR_IEN, base + (I2CR << reg_shift)); in i2c_init_transfer_()
301 writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); in i2c_init_transfer_()
[all …]
Drcar_iic.c92 writeb(priv->iccl, priv->base + RCAR_IIC_ICCL); in rcar_iic_set_addr()
93 writeb(priv->icch, priv->base + RCAR_IIC_ICCH); in rcar_iic_set_addr()
94 writeb(RCAR_IC_TACK, priv->base + RCAR_IIC_ICIC); in rcar_iic_set_addr()
96 writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS | RCAR_IIC_ICCR_BUSY, in rcar_iic_set_addr()
101 writeb(chip << 1 | read, priv->base + RCAR_IIC_ICDR); in rcar_iic_set_addr()
109 writeb(0, priv->base + RCAR_IIC_ICSR); in rcar_iic_finish()
123 writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_SCP, in rcar_iic_read_common()
133 writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RACK, in rcar_iic_read_common()
157 writeb(msg->buf[i], priv->base + RCAR_IIC_ICDR); in rcar_iic_write_common()
163 writeb(RCAR_IIC_ICCR_ICE | RCAR_IIC_ICCR_RTS, in rcar_iic_write_common()
[all …]
/external/u-boot/board/renesas/lager/
Dlager_spl.c324 writeb(0x08, qspi_base + 0x00); in spl_init_qspi()
325 writeb(0x00, qspi_base + 0x01); in spl_init_qspi()
326 writeb(0x06, qspi_base + 0x02); in spl_init_qspi()
327 writeb(0x01, qspi_base + 0x0a); in spl_init_qspi()
328 writeb(0x00, qspi_base + 0x0b); in spl_init_qspi()
329 writeb(0x00, qspi_base + 0x0c); in spl_init_qspi()
330 writeb(0x00, qspi_base + 0x0d); in spl_init_qspi()
331 writeb(0x00, qspi_base + 0x0e); in spl_init_qspi()
335 writeb(0xc0, qspi_base + 0x18); in spl_init_qspi()
336 writeb(0x00, qspi_base + 0x18); in spl_init_qspi()
[all …]
/external/u-boot/drivers/rtc/
Ds3c24x0_rtc.c34 writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); in SetRTC_Access()
38 writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); in SetRTC_Access()
131 writeb(sec, &rtc->bcdsec); in rtc_set()
132 writeb(min, &rtc->bcdmin); in rtc_set()
133 writeb(hour, &rtc->bcdhour); in rtc_set()
134 writeb(mday, &rtc->bcddate); in rtc_set()
135 writeb(wday, &rtc->bcdday); in rtc_set()
136 writeb(mon, &rtc->bcdmon); in rtc_set()
137 writeb(year, &rtc->bcdyear); in rtc_set()
149 writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); in rtc_reset()
[all …]
/external/u-boot/board/renesas/gose/
Dgose_spl.c336 writeb(0x08, qspi_base + 0x00); in spl_init_qspi()
337 writeb(0x00, qspi_base + 0x01); in spl_init_qspi()
338 writeb(0x06, qspi_base + 0x02); in spl_init_qspi()
339 writeb(0x01, qspi_base + 0x0a); in spl_init_qspi()
340 writeb(0x00, qspi_base + 0x0b); in spl_init_qspi()
341 writeb(0x00, qspi_base + 0x0c); in spl_init_qspi()
342 writeb(0x00, qspi_base + 0x0d); in spl_init_qspi()
343 writeb(0x00, qspi_base + 0x0e); in spl_init_qspi()
347 writeb(0xc0, qspi_base + 0x18); in spl_init_qspi()
348 writeb(0x00, qspi_base + 0x18); in spl_init_qspi()
[all …]
/external/u-boot/board/renesas/alt/
Dalt_spl.c342 writeb(0x08, qspi_base + 0x00); in spl_init_qspi()
343 writeb(0x00, qspi_base + 0x01); in spl_init_qspi()
344 writeb(0x06, qspi_base + 0x02); in spl_init_qspi()
345 writeb(0x01, qspi_base + 0x0a); in spl_init_qspi()
346 writeb(0x00, qspi_base + 0x0b); in spl_init_qspi()
347 writeb(0x00, qspi_base + 0x0c); in spl_init_qspi()
348 writeb(0x00, qspi_base + 0x0d); in spl_init_qspi()
349 writeb(0x00, qspi_base + 0x0e); in spl_init_qspi()
353 writeb(0xc0, qspi_base + 0x18); in spl_init_qspi()
354 writeb(0x00, qspi_base + 0x18); in spl_init_qspi()
[all …]
/external/u-boot/drivers/spi/
Dsh_qspi.c83 writeb(SPCR_MSTR, &ss->regs->spcr); in sh_qspi_init()
86 writeb(0x00, &ss->regs->sslp); in sh_qspi_init()
89 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); in sh_qspi_init()
92 writeb(0x01, &ss->regs->spbr); in sh_qspi_init()
95 writeb(0x00, &ss->regs->spdcr); in sh_qspi_init()
98 writeb(0x00, &ss->regs->spckd); in sh_qspi_init()
101 writeb(0x00, &ss->regs->sslnd); in sh_qspi_init()
104 writeb(0x00, &ss->regs->spnd); in sh_qspi_init()
116 writeb(0x00, &ss->regs->spscr); in sh_qspi_init()
132 writeb(SPCR_MSTR, &ss->regs->spcr); in spi_cs_activate()
[all …]
/external/u-boot/board/renesas/koelsch/
Dkoelsch_spl.c331 writeb(0x08, qspi_base + 0x00); in spl_init_qspi()
332 writeb(0x00, qspi_base + 0x01); in spl_init_qspi()
333 writeb(0x06, qspi_base + 0x02); in spl_init_qspi()
334 writeb(0x01, qspi_base + 0x0a); in spl_init_qspi()
335 writeb(0x00, qspi_base + 0x0b); in spl_init_qspi()
336 writeb(0x00, qspi_base + 0x0c); in spl_init_qspi()
337 writeb(0x00, qspi_base + 0x0d); in spl_init_qspi()
338 writeb(0x00, qspi_base + 0x0e); in spl_init_qspi()
342 writeb(0xc0, qspi_base + 0x18); in spl_init_qspi()
343 writeb(0x00, qspi_base + 0x18); in spl_init_qspi()
[all …]
/external/u-boot/board/renesas/silk/
Dsilk_spl.c356 writeb(0x08, qspi_base + 0x00); in spl_init_qspi()
357 writeb(0x00, qspi_base + 0x01); in spl_init_qspi()
358 writeb(0x06, qspi_base + 0x02); in spl_init_qspi()
359 writeb(0x01, qspi_base + 0x0a); in spl_init_qspi()
360 writeb(0x00, qspi_base + 0x0b); in spl_init_qspi()
361 writeb(0x00, qspi_base + 0x0c); in spl_init_qspi()
362 writeb(0x00, qspi_base + 0x0d); in spl_init_qspi()
363 writeb(0x00, qspi_base + 0x0e); in spl_init_qspi()
367 writeb(0xc0, qspi_base + 0x18); in spl_init_qspi()
368 writeb(0x00, qspi_base + 0x18); in spl_init_qspi()
[all …]
/external/u-boot/arch/arm/cpu/arm1136/mx35/
Dmx35_sdram.c89 writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */ in mx3_setup_sdram_bank()
90 writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ in mx3_setup_sdram_bank()
91 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ in mx3_setup_sdram_bank()
92 writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ in mx3_setup_sdram_bank()
107 writeb(0xda, start_address + ESDCTL_DDR2_MR); in mx3_setup_sdram_bank()
108 writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); in mx3_setup_sdram_bank()
111 writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ in mx3_setup_sdram_bank()
/external/u-boot/board/freescale/s32v234evb/
Dclock.c248 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58); in enable_modules_clock()
250 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170); in enable_modules_clock()
252 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83); in enable_modules_clock()
254 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188); in enable_modules_clock()
256 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50); in enable_modules_clock()
258 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93); in enable_modules_clock()
260 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81); in enable_modules_clock()
262 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184); in enable_modules_clock()
264 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186); in enable_modules_clock()
266 writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54); in enable_modules_clock()
[all …]
/external/u-boot/board/renesas/porter/
Dporter_spl.c419 writeb(0x08, qspi_base + 0x00); in spl_init_qspi()
420 writeb(0x00, qspi_base + 0x01); in spl_init_qspi()
421 writeb(0x06, qspi_base + 0x02); in spl_init_qspi()
422 writeb(0x01, qspi_base + 0x0a); in spl_init_qspi()
423 writeb(0x00, qspi_base + 0x0b); in spl_init_qspi()
424 writeb(0x00, qspi_base + 0x0c); in spl_init_qspi()
425 writeb(0x00, qspi_base + 0x0d); in spl_init_qspi()
426 writeb(0x00, qspi_base + 0x0e); in spl_init_qspi()
430 writeb(0xc0, qspi_base + 0x18); in spl_init_qspi()
431 writeb(0x00, qspi_base + 0x18); in spl_init_qspi()
[all …]
/external/u-boot/board/renesas/stout/
Dstout_spl.c405 writeb(0x08, qspi_base + 0x00); in spl_init_qspi()
406 writeb(0x00, qspi_base + 0x01); in spl_init_qspi()
407 writeb(0x06, qspi_base + 0x02); in spl_init_qspi()
408 writeb(0x01, qspi_base + 0x0a); in spl_init_qspi()
409 writeb(0x00, qspi_base + 0x0b); in spl_init_qspi()
410 writeb(0x00, qspi_base + 0x0c); in spl_init_qspi()
411 writeb(0x00, qspi_base + 0x0d); in spl_init_qspi()
412 writeb(0x00, qspi_base + 0x0e); in spl_init_qspi()
416 writeb(0xc0, qspi_base + 0x18); in spl_init_qspi()
417 writeb(0x00, qspi_base + 0x18); in spl_init_qspi()
[all …]
/external/u-boot/drivers/watchdog/
Dulp_wdog.c68 writeb(val, &wdog->cs2); in hw_watchdog_init()
73 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ in hw_watchdog_init()
74 writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ in hw_watchdog_init()
89 writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ in reset_cpu()
90 writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ in reset_cpu()
/external/u-boot/arch/arm/mach-omap2/omap3/
Dspl_id_nand.c38 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
39 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
46 writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
49 writeb(0x0, &gpmc_cfg->cs[0].nand_adr); in identify_nand_chip()

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