1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011
4 * Logic Product Development <www.logicpd.com>
5 *
6 * Author :
7 * Peter Barada <peter.barada@logicpd.com>
8 *
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
12 */
13 #include <common.h>
14 #include <dm.h>
15 #include <ns16550.h>
16 #include <netdev.h>
17 #include <flash.h>
18 #include <nand.h>
19 #include <i2c.h>
20 #include <twl4030.h>
21 #include <asm/io.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/mux.h>
24 #include <asm/arch/mem.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/gpio.h>
27 #include <asm/mach-types.h>
28 #include <linux/mtd/rawnand.h>
29 #include <asm/omap_musb.h>
30 #include <linux/errno.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/musb.h>
34 #include "omap3logic.h"
35 #ifdef CONFIG_USB_EHCI_HCD
36 #include <usb.h>
37 #include <asm/ehci-omap.h>
38 #endif
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 /*
43 * two dimensional array of strucures containining board name and Linux
44 * machine IDs; row it selected based on CPU column is slected based
45 * on hsusb0_data5 pin having a pulldown resistor
46 */
47 static struct board_id {
48 char *name;
49 int machine_id;
50 char *fdtfile;
51 } boards[2][2] = {
52 {
53 {
54 .name = "OMAP35xx SOM LV",
55 .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
56 .fdtfile = "logicpd-som-lv-35xx-devkit.dtb",
57 },
58 {
59 .name = "OMAP35xx Torpedo",
60 .machine_id = MACH_TYPE_OMAP3_TORPEDO,
61 .fdtfile = "logicpd-torpedo-35xx-devkit.dtb",
62 },
63 },
64 {
65 {
66 .name = "DM37xx SOM LV",
67 .fdtfile = "logicpd-som-lv-37xx-devkit.dtb",
68 },
69 {
70 .name = "DM37xx Torpedo",
71 .fdtfile = "logicpd-torpedo-37xx-devkit.dtb",
72 },
73 },
74 };
75
76 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)77 int spl_start_uboot(void)
78 {
79 /* break into full u-boot on 'c' */
80 return serial_tstc() && serial_getc() == 'c';
81 }
82 #endif
83
84 #if defined(CONFIG_SPL_BUILD)
85 /*
86 * Routine: get_board_mem_timings
87 * Description: If we use SPL then there is no x-loader nor config header
88 * so we have to setup the DDR timings ourself on the first bank. This
89 * provides the timing values back to the function that configures
90 * the memory.
91 */
get_board_mem_timings(struct board_sdrc_timings * timings)92 void get_board_mem_timings(struct board_sdrc_timings *timings)
93 {
94 timings->mr = MICRON_V_MR_165;
95 /* 256MB DDR */
96 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
97 timings->ctrla = MICRON_V_ACTIMA_200;
98 timings->ctrlb = MICRON_V_ACTIMB_200;
99 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
100 }
101
102 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
103 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
104 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
105
spl_board_prepare_for_linux(void)106 void spl_board_prepare_for_linux(void)
107 {
108 /* The Micron NAND starts locked which
109 * prohibits mounting the NAND as RW
110 * The following commands are what unlocks
111 * the NAND to become RW Falcon Mode does not
112 * have as many smarts as U-Boot, but Logic PD
113 * only makes NAND with 512MB so these hard coded
114 * values should work for all current models
115 */
116
117 writeb(0x70, GPMC_NAND_COMMAND_0);
118 writeb(-1, GPMC_NAND_DATA_0);
119 writeb(0x7a, GPMC_NAND_COMMAND_0);
120 writeb(0x00, GPMC_NAND_ADDRESS_0);
121 writeb(0x00, GPMC_NAND_ADDRESS_0);
122 writeb(0x00, GPMC_NAND_ADDRESS_0);
123 writeb(-1, GPMC_NAND_COMMAND_0);
124
125 /* Begin address 0 */
126 writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
127 writeb(0x00, GPMC_NAND_ADDRESS_0);
128 writeb(0x00, GPMC_NAND_ADDRESS_0);
129 writeb(0x00, GPMC_NAND_ADDRESS_0);
130 writeb(-1, GPMC_NAND_DATA_0);
131
132 /* Ending address at the end of Flash */
133 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
134 writeb(0xc0, GPMC_NAND_ADDRESS_0);
135 writeb(0xff, GPMC_NAND_ADDRESS_0);
136 writeb(0x03, GPMC_NAND_ADDRESS_0);
137 writeb(-1, GPMC_NAND_DATA_0);
138 writeb(0x79, GPMC_NAND_COMMAND_0);
139 writeb(-1, GPMC_NAND_DATA_0);
140 writeb(-1, GPMC_NAND_DATA_0);
141 }
142 #endif
143
144 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
145 static struct musb_hdrc_config musb_config = {
146 .multipoint = 1,
147 .dyn_fifo = 1,
148 .num_eps = 16,
149 .ram_bits = 12,
150 };
151
152 static struct omap_musb_board_data musb_board_data = {
153 .interface_type = MUSB_INTERFACE_ULPI,
154 };
155
156 static struct musb_hdrc_platform_data musb_plat = {
157 #if defined(CONFIG_USB_MUSB_HOST)
158 .mode = MUSB_HOST,
159 #elif defined(CONFIG_USB_MUSB_GADGET)
160 .mode = MUSB_PERIPHERAL,
161 #else
162 #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
163 #endif
164 .config = &musb_config,
165 .power = 100,
166 .platform_ops = &omap2430_ops,
167 .board_data = &musb_board_data,
168 };
169 #endif
170
171 #if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
172 /* Call usb_stop() before starting the kernel */
show_boot_progress(int val)173 void show_boot_progress(int val)
174 {
175 if (val == BOOTSTAGE_ID_RUN_OS)
176 usb_stop();
177 }
178
179 static struct omap_usbhs_board_data usbhs_bdata = {
180 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
181 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
182 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
183 };
184
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)185 int ehci_hcd_init(int index, enum usb_init_type init,
186 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
187 {
188 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
189 }
190
ehci_hcd_stop(int index)191 int ehci_hcd_stop(int index)
192 {
193 return omap_ehci_hcd_stop();
194 }
195
196 #endif /* CONFIG_USB_EHCI_HCD */
197
198
199 /*
200 * Routine: misc_init_r
201 * Description: Configure board specific parts
202 */
misc_init_r(void)203 int misc_init_r(void)
204 {
205 twl4030_power_init();
206 omap_die_id_display();
207
208 #ifdef CONFIG_USB_MUSB_OMAP2PLUS
209 musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
210 #endif
211
212 return 0;
213 }
214
215 /*
216 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
217 */
218 #define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
219
220 /*
221 * Routine: board_init
222 * Description: Early hardware init.
223 */
board_init(void)224 int board_init(void)
225 {
226 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
227
228 /* boot param addr */
229 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
230
231 return 0;
232 }
233
234 #ifdef CONFIG_BOARD_LATE_INIT
235
unlock_nand(void)236 static void unlock_nand(void)
237 {
238 int dev = nand_curr_device;
239 struct mtd_info *mtd;
240
241 mtd = get_nand_dev_by_index(dev);
242 nand_unlock(mtd, 0, mtd->size, 0);
243 }
244
board_late_init(void)245 int board_late_init(void)
246 {
247 struct board_id *board;
248 unsigned int val;
249
250 /*
251 * To identify between a SOM LV and Torpedo module,
252 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
253 * Drive the pin (and let it soak), then read it back.
254 * If the pin is still high its a Torpedo. If low its a SOM LV
255 */
256
257 /* Mux hsusb0_data5 as a GPIO */
258 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
259
260 if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
261
262 /*
263 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
264 * will drain the voltage.
265 */
266 gpio_direction_output(BOARD_ID_GPIO, 0);
267 gpio_set_value(BOARD_ID_GPIO, 1);
268
269 /* Let it soak for a bit */
270 sdelay(0x100);
271
272 /*
273 * Read state of BOARD_ID_GPIO as an input and if its set.
274 * If so the board is a Torpedo
275 */
276 gpio_direction_input(BOARD_ID_GPIO);
277 val = gpio_get_value(BOARD_ID_GPIO);
278 gpio_free(BOARD_ID_GPIO);
279
280 board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
281 printf("Board: %s\n", board->name);
282
283 /* Set the machine_id passed to Linux */
284 if (board->machine_id)
285 gd->bd->bi_arch_number = board->machine_id;
286
287 /* If the user has not set fdtimage, set the default */
288 if (!env_get("fdtimage"))
289 env_set("fdtimage", board->fdtfile);
290 }
291
292 /* restore hsusb0_data5 pin as hsusb0_data5 */
293 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
294
295 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
296 unlock_nand();
297 #endif
298 return 0;
299 }
300 #endif
301
302 #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)303 int board_mmc_init(bd_t *bis)
304 {
305 return omap_mmc_init(0, 0, 0, -1, -1);
306 }
307 #endif
308
309 #if defined(CONFIG_MMC)
board_mmc_power_init(void)310 void board_mmc_power_init(void)
311 {
312 twl4030_power_mmc_init(0);
313 }
314 #endif
315
316 #ifdef CONFIG_SMC911X
317 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
318 static const u32 gpmc_lan92xx_config[] = {
319 NET_LAN92XX_GPMC_CONFIG1,
320 NET_LAN92XX_GPMC_CONFIG2,
321 NET_LAN92XX_GPMC_CONFIG3,
322 NET_LAN92XX_GPMC_CONFIG4,
323 NET_LAN92XX_GPMC_CONFIG5,
324 NET_LAN92XX_GPMC_CONFIG6,
325 };
326
board_eth_init(bd_t * bis)327 int board_eth_init(bd_t *bis)
328 {
329 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
330 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
331
332 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
333 }
334 #endif
335
336
337