Home
last modified time | relevance | path

Searched refs:zq0cr1 (Results 1 – 12 of 12) sorted by relevance

/external/u-boot/board/ti/ks2_evm/
Dddr3_k2g.c35 .zq0cr1 = 0x0001005Dul,
75 .zq0cr1 = 0x0001005Dul,
136 .zq0cr1 = 0x0001005Dul,
Dddr3_cfg.c33 .zq0cr1 = 0x0001005Dul,
Dddr3_k2e.c38 spd_cb.phy_cfg.zq0cr1 |= 0x10000; in ddr3_init()
Dddr3_k2hk.c45 spd_cb.phy_cfg.zq0cr1 |= 0x10000; in ddr3_init()
/external/u-boot/arch/arm/mach-keystone/include/mach/
Dddr3.h33 unsigned int zq0cr1; member
/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr.h123 u32 zq0cr1; member
Dstm32mp1_ddr_regs.h196 u32 zq0cr1; /* 0x184 zq 0 control 1 */ member
Dstm32mp1_ddr.c131 DDRPHY_REG_REG(zq0cr1),
/external/u-boot/arch/arm/mach-keystone/
Dddr3_spd.c39 debug_ddr_cfg("zq0cr1 0x%08X\n", ptr->zq0cr1); in dump_phy_config()
361 spd_cb->phy_cfg.zq0cr1 = 0x0000005D; in init_ddr3param()
Dddr3.c58 __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); in ddr3_init_ddrphy()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun6i.h210 u32 zq0cr1; /* 0x184 zq 0 control register 1 */ member
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun6i.c157 writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1); in mctl_channel_init()