1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_I915_DRM_H_ 20 #define _UAPI_I915_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 26 #define I915_ERROR_UEVENT "ERROR" 27 #define I915_RESET_UEVENT "RESET" 28 enum i915_mocs_table_index { 29 I915_MOCS_UNCACHED, 30 I915_MOCS_PTE, 31 I915_MOCS_CACHED, 32 }; 33 enum drm_i915_gem_engine_class { 34 I915_ENGINE_CLASS_RENDER = 0, 35 I915_ENGINE_CLASS_COPY = 1, 36 I915_ENGINE_CLASS_VIDEO = 2, 37 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 38 I915_ENGINE_CLASS_INVALID = - 1 39 }; 40 enum drm_i915_pmu_engine_sample { 41 I915_SAMPLE_BUSY = 0, 42 I915_SAMPLE_WAIT = 1, 43 I915_SAMPLE_SEMA = 2 44 }; 45 #define I915_PMU_SAMPLE_BITS (4) 46 #define I915_PMU_SAMPLE_MASK (0xf) 47 #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 48 #define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 49 #define __I915_PMU_ENGINE(class,instance,sample) ((class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample)) 50 #define I915_PMU_ENGINE_BUSY(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 51 #define I915_PMU_ENGINE_WAIT(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 52 #define I915_PMU_ENGINE_SEMA(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 53 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 54 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 55 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 56 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 57 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 58 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 59 #define I915_NR_TEX_REGIONS 255 60 #define I915_LOG_MIN_TEX_REGION_SIZE 14 61 typedef struct _drm_i915_init { 62 enum { 63 I915_INIT_DMA = 0x01, 64 I915_CLEANUP_DMA = 0x02, 65 I915_RESUME_DMA = 0x03 66 } func; 67 unsigned int mmio_offset; 68 int sarea_priv_offset; 69 unsigned int ring_start; 70 unsigned int ring_end; 71 unsigned int ring_size; 72 unsigned int front_offset; 73 unsigned int back_offset; 74 unsigned int depth_offset; 75 unsigned int w; 76 unsigned int h; 77 unsigned int pitch; 78 unsigned int pitch_bits; 79 unsigned int back_pitch; 80 unsigned int depth_pitch; 81 unsigned int cpp; 82 unsigned int chipset; 83 } drm_i915_init_t; 84 typedef struct _drm_i915_sarea { 85 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 86 int last_upload; 87 int last_enqueue; 88 int last_dispatch; 89 int ctxOwner; 90 int texAge; 91 int pf_enabled; 92 int pf_active; 93 int pf_current_page; 94 int perf_boxes; 95 int width, height; 96 drm_handle_t front_handle; 97 int front_offset; 98 int front_size; 99 drm_handle_t back_handle; 100 int back_offset; 101 int back_size; 102 drm_handle_t depth_handle; 103 int depth_offset; 104 int depth_size; 105 drm_handle_t tex_handle; 106 int tex_offset; 107 int tex_size; 108 int log_tex_granularity; 109 int pitch; 110 int rotation; 111 int rotated_offset; 112 int rotated_size; 113 int rotated_pitch; 114 int virtualX, virtualY; 115 unsigned int front_tiled; 116 unsigned int back_tiled; 117 unsigned int depth_tiled; 118 unsigned int rotated_tiled; 119 unsigned int rotated2_tiled; 120 int pipeA_x; 121 int pipeA_y; 122 int pipeA_w; 123 int pipeA_h; 124 int pipeB_x; 125 int pipeB_y; 126 int pipeB_w; 127 int pipeB_h; 128 drm_handle_t unused_handle; 129 __u32 unused1, unused2, unused3; 130 __u32 front_bo_handle; 131 __u32 back_bo_handle; 132 __u32 unused_bo_handle; 133 __u32 depth_bo_handle; 134 } drm_i915_sarea_t; 135 #define planeA_x pipeA_x 136 #define planeA_y pipeA_y 137 #define planeA_w pipeA_w 138 #define planeA_h pipeA_h 139 #define planeB_x pipeB_x 140 #define planeB_y pipeB_y 141 #define planeB_w pipeB_w 142 #define planeB_h pipeB_h 143 #define I915_BOX_RING_EMPTY 0x1 144 #define I915_BOX_FLIP 0x2 145 #define I915_BOX_WAIT 0x4 146 #define I915_BOX_TEXTURE_LOAD 0x8 147 #define I915_BOX_LOST_CONTEXT 0x10 148 #define DRM_I915_INIT 0x00 149 #define DRM_I915_FLUSH 0x01 150 #define DRM_I915_FLIP 0x02 151 #define DRM_I915_BATCHBUFFER 0x03 152 #define DRM_I915_IRQ_EMIT 0x04 153 #define DRM_I915_IRQ_WAIT 0x05 154 #define DRM_I915_GETPARAM 0x06 155 #define DRM_I915_SETPARAM 0x07 156 #define DRM_I915_ALLOC 0x08 157 #define DRM_I915_FREE 0x09 158 #define DRM_I915_INIT_HEAP 0x0a 159 #define DRM_I915_CMDBUFFER 0x0b 160 #define DRM_I915_DESTROY_HEAP 0x0c 161 #define DRM_I915_SET_VBLANK_PIPE 0x0d 162 #define DRM_I915_GET_VBLANK_PIPE 0x0e 163 #define DRM_I915_VBLANK_SWAP 0x0f 164 #define DRM_I915_HWS_ADDR 0x11 165 #define DRM_I915_GEM_INIT 0x13 166 #define DRM_I915_GEM_EXECBUFFER 0x14 167 #define DRM_I915_GEM_PIN 0x15 168 #define DRM_I915_GEM_UNPIN 0x16 169 #define DRM_I915_GEM_BUSY 0x17 170 #define DRM_I915_GEM_THROTTLE 0x18 171 #define DRM_I915_GEM_ENTERVT 0x19 172 #define DRM_I915_GEM_LEAVEVT 0x1a 173 #define DRM_I915_GEM_CREATE 0x1b 174 #define DRM_I915_GEM_PREAD 0x1c 175 #define DRM_I915_GEM_PWRITE 0x1d 176 #define DRM_I915_GEM_MMAP 0x1e 177 #define DRM_I915_GEM_SET_DOMAIN 0x1f 178 #define DRM_I915_GEM_SW_FINISH 0x20 179 #define DRM_I915_GEM_SET_TILING 0x21 180 #define DRM_I915_GEM_GET_TILING 0x22 181 #define DRM_I915_GEM_GET_APERTURE 0x23 182 #define DRM_I915_GEM_MMAP_GTT 0x24 183 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 184 #define DRM_I915_GEM_MADVISE 0x26 185 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 186 #define DRM_I915_OVERLAY_ATTRS 0x28 187 #define DRM_I915_GEM_EXECBUFFER2 0x29 188 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 189 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 190 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 191 #define DRM_I915_GEM_WAIT 0x2c 192 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 193 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 194 #define DRM_I915_GEM_SET_CACHING 0x2f 195 #define DRM_I915_GEM_GET_CACHING 0x30 196 #define DRM_I915_REG_READ 0x31 197 #define DRM_I915_GET_RESET_STATS 0x32 198 #define DRM_I915_GEM_USERPTR 0x33 199 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 200 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 201 #define DRM_I915_PERF_OPEN 0x36 202 #define DRM_I915_PERF_ADD_CONFIG 0x37 203 #define DRM_I915_PERF_REMOVE_CONFIG 0x38 204 #define DRM_I915_QUERY 0x39 205 #define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 206 #define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 207 #define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 208 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 209 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 210 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 211 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 212 #define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 213 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 214 #define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 215 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 216 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 217 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 218 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 219 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 220 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 221 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 222 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 223 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 224 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 225 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 226 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 227 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 228 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 229 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 230 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 231 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 232 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 233 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 234 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 235 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 236 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 237 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 238 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 239 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 240 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 241 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 242 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 243 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 244 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 245 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 246 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 247 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 248 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 249 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 250 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 251 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 252 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 253 #define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 254 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 255 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 256 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 257 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 258 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 259 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 260 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 261 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 262 typedef struct drm_i915_batchbuffer { 263 int start; 264 int used; 265 int DR1; 266 int DR4; 267 int num_cliprects; 268 struct drm_clip_rect __user * cliprects; 269 } drm_i915_batchbuffer_t; 270 typedef struct _drm_i915_cmdbuffer { 271 char __user * buf; 272 int sz; 273 int DR1; 274 int DR4; 275 int num_cliprects; 276 struct drm_clip_rect __user * cliprects; 277 } drm_i915_cmdbuffer_t; 278 typedef struct drm_i915_irq_emit { 279 int __user * irq_seq; 280 } drm_i915_irq_emit_t; 281 typedef struct drm_i915_irq_wait { 282 int irq_seq; 283 } drm_i915_irq_wait_t; 284 #define I915_GEM_PPGTT_NONE 0 285 #define I915_GEM_PPGTT_ALIASING 1 286 #define I915_GEM_PPGTT_FULL 2 287 #define I915_PARAM_IRQ_ACTIVE 1 288 #define I915_PARAM_ALLOW_BATCHBUFFER 2 289 #define I915_PARAM_LAST_DISPATCH 3 290 #define I915_PARAM_CHIPSET_ID 4 291 #define I915_PARAM_HAS_GEM 5 292 #define I915_PARAM_NUM_FENCES_AVAIL 6 293 #define I915_PARAM_HAS_OVERLAY 7 294 #define I915_PARAM_HAS_PAGEFLIPPING 8 295 #define I915_PARAM_HAS_EXECBUF2 9 296 #define I915_PARAM_HAS_BSD 10 297 #define I915_PARAM_HAS_BLT 11 298 #define I915_PARAM_HAS_RELAXED_FENCING 12 299 #define I915_PARAM_HAS_COHERENT_RINGS 13 300 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 301 #define I915_PARAM_HAS_RELAXED_DELTA 15 302 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 303 #define I915_PARAM_HAS_LLC 17 304 #define I915_PARAM_HAS_ALIASING_PPGTT 18 305 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 306 #define I915_PARAM_HAS_SEMAPHORES 20 307 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 308 #define I915_PARAM_HAS_VEBOX 22 309 #define I915_PARAM_HAS_SECURE_BATCHES 23 310 #define I915_PARAM_HAS_PINNED_BATCHES 24 311 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 312 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 313 #define I915_PARAM_HAS_WT 27 314 #define I915_PARAM_CMD_PARSER_VERSION 28 315 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 316 #define I915_PARAM_MMAP_VERSION 30 317 #define I915_PARAM_HAS_BSD2 31 318 #define I915_PARAM_REVISION 32 319 #define I915_PARAM_SUBSLICE_TOTAL 33 320 #define I915_PARAM_EU_TOTAL 34 321 #define I915_PARAM_HAS_GPU_RESET 35 322 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 323 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 324 #define I915_PARAM_HAS_POOLED_EU 38 325 #define I915_PARAM_MIN_EU_IN_POOL 39 326 #define I915_PARAM_MMAP_GTT_VERSION 40 327 #define I915_PARAM_HAS_SCHEDULER 41 328 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 329 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 330 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 331 #define I915_PARAM_HUC_STATUS 42 332 #define I915_PARAM_HAS_EXEC_ASYNC 43 333 #define I915_PARAM_HAS_EXEC_FENCE 44 334 #define I915_PARAM_HAS_EXEC_CAPTURE 45 335 #define I915_PARAM_SLICE_MASK 46 336 #define I915_PARAM_SUBSLICE_MASK 47 337 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 338 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 339 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 340 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 341 #define I915_PARAM_MMAP_GTT_COHERENT 52 342 typedef struct drm_i915_getparam { 343 __s32 param; 344 int __user * value; 345 } drm_i915_getparam_t; 346 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 347 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 348 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 349 #define I915_SETPARAM_NUM_USED_FENCES 4 350 typedef struct drm_i915_setparam { 351 int param; 352 int value; 353 } drm_i915_setparam_t; 354 #define I915_MEM_REGION_AGP 1 355 typedef struct drm_i915_mem_alloc { 356 int region; 357 int alignment; 358 int size; 359 int __user * region_offset; 360 } drm_i915_mem_alloc_t; 361 typedef struct drm_i915_mem_free { 362 int region; 363 int region_offset; 364 } drm_i915_mem_free_t; 365 typedef struct drm_i915_mem_init_heap { 366 int region; 367 int size; 368 int start; 369 } drm_i915_mem_init_heap_t; 370 typedef struct drm_i915_mem_destroy_heap { 371 int region; 372 } drm_i915_mem_destroy_heap_t; 373 #define DRM_I915_VBLANK_PIPE_A 1 374 #define DRM_I915_VBLANK_PIPE_B 2 375 typedef struct drm_i915_vblank_pipe { 376 int pipe; 377 } drm_i915_vblank_pipe_t; 378 typedef struct drm_i915_vblank_swap { 379 drm_drawable_t drawable; 380 enum drm_vblank_seq_type seqtype; 381 unsigned int sequence; 382 } drm_i915_vblank_swap_t; 383 typedef struct drm_i915_hws_addr { 384 __u64 addr; 385 } drm_i915_hws_addr_t; 386 struct drm_i915_gem_init { 387 __u64 gtt_start; 388 __u64 gtt_end; 389 }; 390 struct drm_i915_gem_create { 391 __u64 size; 392 __u32 handle; 393 __u32 pad; 394 }; 395 struct drm_i915_gem_pread { 396 __u32 handle; 397 __u32 pad; 398 __u64 offset; 399 __u64 size; 400 __u64 data_ptr; 401 }; 402 struct drm_i915_gem_pwrite { 403 __u32 handle; 404 __u32 pad; 405 __u64 offset; 406 __u64 size; 407 __u64 data_ptr; 408 }; 409 struct drm_i915_gem_mmap { 410 __u32 handle; 411 __u32 pad; 412 __u64 offset; 413 __u64 size; 414 __u64 addr_ptr; 415 __u64 flags; 416 #define I915_MMAP_WC 0x1 417 }; 418 struct drm_i915_gem_mmap_gtt { 419 __u32 handle; 420 __u32 pad; 421 __u64 offset; 422 }; 423 struct drm_i915_gem_set_domain { 424 __u32 handle; 425 __u32 read_domains; 426 __u32 write_domain; 427 }; 428 struct drm_i915_gem_sw_finish { 429 __u32 handle; 430 }; 431 struct drm_i915_gem_relocation_entry { 432 __u32 target_handle; 433 __u32 delta; 434 __u64 offset; 435 __u64 presumed_offset; 436 __u32 read_domains; 437 __u32 write_domain; 438 }; 439 #define I915_GEM_DOMAIN_CPU 0x00000001 440 #define I915_GEM_DOMAIN_RENDER 0x00000002 441 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 442 #define I915_GEM_DOMAIN_COMMAND 0x00000008 443 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 444 #define I915_GEM_DOMAIN_VERTEX 0x00000020 445 #define I915_GEM_DOMAIN_GTT 0x00000040 446 #define I915_GEM_DOMAIN_WC 0x00000080 447 struct drm_i915_gem_exec_object { 448 __u32 handle; 449 __u32 relocation_count; 450 __u64 relocs_ptr; 451 __u64 alignment; 452 __u64 offset; 453 }; 454 struct drm_i915_gem_execbuffer { 455 __u64 buffers_ptr; 456 __u32 buffer_count; 457 __u32 batch_start_offset; 458 __u32 batch_len; 459 __u32 DR1; 460 __u32 DR4; 461 __u32 num_cliprects; 462 __u64 cliprects_ptr; 463 }; 464 struct drm_i915_gem_exec_object2 { 465 __u32 handle; 466 __u32 relocation_count; 467 __u64 relocs_ptr; 468 __u64 alignment; 469 __u64 offset; 470 #define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 471 #define EXEC_OBJECT_NEEDS_GTT (1 << 1) 472 #define EXEC_OBJECT_WRITE (1 << 2) 473 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 474 #define EXEC_OBJECT_PINNED (1 << 4) 475 #define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 476 #define EXEC_OBJECT_ASYNC (1 << 6) 477 #define EXEC_OBJECT_CAPTURE (1 << 7) 478 #define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_CAPTURE << 1) 479 __u64 flags; 480 union { 481 __u64 rsvd1; 482 __u64 pad_to_size; 483 }; 484 __u64 rsvd2; 485 }; 486 struct drm_i915_gem_exec_fence { 487 __u32 handle; 488 #define I915_EXEC_FENCE_WAIT (1 << 0) 489 #define I915_EXEC_FENCE_SIGNAL (1 << 1) 490 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SIGNAL << 1)) 491 __u32 flags; 492 }; 493 struct drm_i915_gem_execbuffer2 { 494 __u64 buffers_ptr; 495 __u32 buffer_count; 496 __u32 batch_start_offset; 497 __u32 batch_len; 498 __u32 DR1; 499 __u32 DR4; 500 __u32 num_cliprects; 501 __u64 cliprects_ptr; 502 #define I915_EXEC_RING_MASK (7 << 0) 503 #define I915_EXEC_DEFAULT (0 << 0) 504 #define I915_EXEC_RENDER (1 << 0) 505 #define I915_EXEC_BSD (2 << 0) 506 #define I915_EXEC_BLT (3 << 0) 507 #define I915_EXEC_VEBOX (4 << 0) 508 #define I915_EXEC_CONSTANTS_MASK (3 << 6) 509 #define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 510 #define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 511 #define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 512 __u64 flags; 513 __u64 rsvd1; 514 __u64 rsvd2; 515 }; 516 #define I915_EXEC_GEN7_SOL_RESET (1 << 8) 517 #define I915_EXEC_SECURE (1 << 9) 518 #define I915_EXEC_IS_PINNED (1 << 10) 519 #define I915_EXEC_NO_RELOC (1 << 11) 520 #define I915_EXEC_HANDLE_LUT (1 << 12) 521 #define I915_EXEC_BSD_SHIFT (13) 522 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 523 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 524 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 525 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 526 #define I915_EXEC_RESOURCE_STREAMER (1 << 15) 527 #define I915_EXEC_FENCE_IN (1 << 16) 528 #define I915_EXEC_FENCE_OUT (1 << 17) 529 #define I915_EXEC_BATCH_FIRST (1 << 18) 530 #define I915_EXEC_FENCE_ARRAY (1 << 19) 531 #define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_ARRAY << 1)) 532 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 533 #define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 534 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 535 struct drm_i915_gem_pin { 536 __u32 handle; 537 __u32 pad; 538 __u64 alignment; 539 __u64 offset; 540 }; 541 struct drm_i915_gem_unpin { 542 __u32 handle; 543 __u32 pad; 544 }; 545 struct drm_i915_gem_busy { 546 __u32 handle; 547 __u32 busy; 548 }; 549 #define I915_CACHING_NONE 0 550 #define I915_CACHING_CACHED 1 551 #define I915_CACHING_DISPLAY 2 552 struct drm_i915_gem_caching { 553 __u32 handle; 554 __u32 caching; 555 }; 556 #define I915_TILING_NONE 0 557 #define I915_TILING_X 1 558 #define I915_TILING_Y 2 559 #define I915_TILING_LAST I915_TILING_Y 560 #define I915_BIT_6_SWIZZLE_NONE 0 561 #define I915_BIT_6_SWIZZLE_9 1 562 #define I915_BIT_6_SWIZZLE_9_10 2 563 #define I915_BIT_6_SWIZZLE_9_11 3 564 #define I915_BIT_6_SWIZZLE_9_10_11 4 565 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 566 #define I915_BIT_6_SWIZZLE_9_17 6 567 #define I915_BIT_6_SWIZZLE_9_10_17 7 568 struct drm_i915_gem_set_tiling { 569 __u32 handle; 570 __u32 tiling_mode; 571 __u32 stride; 572 __u32 swizzle_mode; 573 }; 574 struct drm_i915_gem_get_tiling { 575 __u32 handle; 576 __u32 tiling_mode; 577 __u32 swizzle_mode; 578 __u32 phys_swizzle_mode; 579 }; 580 struct drm_i915_gem_get_aperture { 581 __u64 aper_size; 582 __u64 aper_available_size; 583 }; 584 struct drm_i915_get_pipe_from_crtc_id { 585 __u32 crtc_id; 586 __u32 pipe; 587 }; 588 #define I915_MADV_WILLNEED 0 589 #define I915_MADV_DONTNEED 1 590 #define __I915_MADV_PURGED 2 591 struct drm_i915_gem_madvise { 592 __u32 handle; 593 __u32 madv; 594 __u32 retained; 595 }; 596 #define I915_OVERLAY_TYPE_MASK 0xff 597 #define I915_OVERLAY_YUV_PLANAR 0x01 598 #define I915_OVERLAY_YUV_PACKED 0x02 599 #define I915_OVERLAY_RGB 0x03 600 #define I915_OVERLAY_DEPTH_MASK 0xff00 601 #define I915_OVERLAY_RGB24 0x1000 602 #define I915_OVERLAY_RGB16 0x2000 603 #define I915_OVERLAY_RGB15 0x3000 604 #define I915_OVERLAY_YUV422 0x0100 605 #define I915_OVERLAY_YUV411 0x0200 606 #define I915_OVERLAY_YUV420 0x0300 607 #define I915_OVERLAY_YUV410 0x0400 608 #define I915_OVERLAY_SWAP_MASK 0xff0000 609 #define I915_OVERLAY_NO_SWAP 0x000000 610 #define I915_OVERLAY_UV_SWAP 0x010000 611 #define I915_OVERLAY_Y_SWAP 0x020000 612 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 613 #define I915_OVERLAY_FLAGS_MASK 0xff000000 614 #define I915_OVERLAY_ENABLE 0x01000000 615 struct drm_intel_overlay_put_image { 616 __u32 flags; 617 __u32 bo_handle; 618 __u16 stride_Y; 619 __u16 stride_UV; 620 __u32 offset_Y; 621 __u32 offset_U; 622 __u32 offset_V; 623 __u16 src_width; 624 __u16 src_height; 625 __u16 src_scan_width; 626 __u16 src_scan_height; 627 __u32 crtc_id; 628 __u16 dst_x; 629 __u16 dst_y; 630 __u16 dst_width; 631 __u16 dst_height; 632 }; 633 #define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 634 #define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 635 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 636 struct drm_intel_overlay_attrs { 637 __u32 flags; 638 __u32 color_key; 639 __s32 brightness; 640 __u32 contrast; 641 __u32 saturation; 642 __u32 gamma0; 643 __u32 gamma1; 644 __u32 gamma2; 645 __u32 gamma3; 646 __u32 gamma4; 647 __u32 gamma5; 648 }; 649 #define I915_SET_COLORKEY_NONE (1 << 0) 650 #define I915_SET_COLORKEY_DESTINATION (1 << 1) 651 #define I915_SET_COLORKEY_SOURCE (1 << 2) 652 struct drm_intel_sprite_colorkey { 653 __u32 plane_id; 654 __u32 min_value; 655 __u32 channel_mask; 656 __u32 max_value; 657 __u32 flags; 658 }; 659 struct drm_i915_gem_wait { 660 __u32 bo_handle; 661 __u32 flags; 662 __s64 timeout_ns; 663 }; 664 struct drm_i915_gem_context_create { 665 __u32 ctx_id; 666 __u32 pad; 667 }; 668 struct drm_i915_gem_context_destroy { 669 __u32 ctx_id; 670 __u32 pad; 671 }; 672 struct drm_i915_reg_read { 673 __u64 offset; 674 #define I915_REG_READ_8B_WA (1ul << 0) 675 __u64 val; 676 }; 677 struct drm_i915_reset_stats { 678 __u32 ctx_id; 679 __u32 flags; 680 __u32 reset_count; 681 __u32 batch_active; 682 __u32 batch_pending; 683 __u32 pad; 684 }; 685 struct drm_i915_gem_userptr { 686 __u64 user_ptr; 687 __u64 user_size; 688 __u32 flags; 689 #define I915_USERPTR_READ_ONLY 0x1 690 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 691 __u32 handle; 692 }; 693 struct drm_i915_gem_context_param { 694 __u32 ctx_id; 695 __u32 size; 696 __u64 param; 697 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 698 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 699 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 700 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 701 #define I915_CONTEXT_PARAM_BANNABLE 0x5 702 #define I915_CONTEXT_PARAM_PRIORITY 0x6 703 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 704 #define I915_CONTEXT_DEFAULT_PRIORITY 0 705 #define I915_CONTEXT_MIN_USER_PRIORITY - 1023 706 __u64 value; 707 }; 708 enum drm_i915_oa_format { 709 I915_OA_FORMAT_A13 = 1, 710 I915_OA_FORMAT_A29, 711 I915_OA_FORMAT_A13_B8_C8, 712 I915_OA_FORMAT_B4_C8, 713 I915_OA_FORMAT_A45_B8_C8, 714 I915_OA_FORMAT_B4_C8_A16, 715 I915_OA_FORMAT_C4_B8, 716 I915_OA_FORMAT_A12, 717 I915_OA_FORMAT_A12_B8_C8, 718 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 719 I915_OA_FORMAT_MAX 720 }; 721 enum drm_i915_perf_property_id { 722 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 723 DRM_I915_PERF_PROP_SAMPLE_OA, 724 DRM_I915_PERF_PROP_OA_METRICS_SET, 725 DRM_I915_PERF_PROP_OA_FORMAT, 726 DRM_I915_PERF_PROP_OA_EXPONENT, 727 DRM_I915_PERF_PROP_MAX 728 }; 729 struct drm_i915_perf_open_param { 730 __u32 flags; 731 #define I915_PERF_FLAG_FD_CLOEXEC (1 << 0) 732 #define I915_PERF_FLAG_FD_NONBLOCK (1 << 1) 733 #define I915_PERF_FLAG_DISABLED (1 << 2) 734 __u32 num_properties; 735 __u64 properties_ptr; 736 }; 737 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 738 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 739 struct drm_i915_perf_record_header { 740 __u32 type; 741 __u16 pad; 742 __u16 size; 743 }; 744 enum drm_i915_perf_record_type { 745 DRM_I915_PERF_RECORD_SAMPLE = 1, 746 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 747 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 748 DRM_I915_PERF_RECORD_MAX 749 }; 750 struct drm_i915_perf_oa_config { 751 char uuid[36]; 752 __u32 n_mux_regs; 753 __u32 n_boolean_regs; 754 __u32 n_flex_regs; 755 __u64 mux_regs_ptr; 756 __u64 boolean_regs_ptr; 757 __u64 flex_regs_ptr; 758 }; 759 struct drm_i915_query_item { 760 __u64 query_id; 761 #define DRM_I915_QUERY_TOPOLOGY_INFO 1 762 __s32 length; 763 __u32 flags; 764 __u64 data_ptr; 765 }; 766 struct drm_i915_query { 767 __u32 num_items; 768 __u32 flags; 769 __u64 items_ptr; 770 }; 771 struct drm_i915_query_topology_info { 772 __u16 flags; 773 __u16 max_slices; 774 __u16 max_subslices; 775 __u16 max_eus_per_subslice; 776 __u16 subslice_offset; 777 __u16 subslice_stride; 778 __u16 eu_offset; 779 __u16 eu_stride; 780 __u8 data[]; 781 }; 782 #ifdef __cplusplus 783 } 784 #endif 785 #endif 786