1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define MSM_PIPE_NONE 0x00 26 #define MSM_PIPE_2D0 0x01 27 #define MSM_PIPE_2D1 0x02 28 #define MSM_PIPE_3D0 0x10 29 #define MSM_PIPE_ID_MASK 0xffff 30 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 31 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 32 struct drm_msm_timespec { 33 __s64 tv_sec; 34 __s64 tv_nsec; 35 }; 36 #define MSM_PARAM_GPU_ID 0x01 37 #define MSM_PARAM_GMEM_SIZE 0x02 38 #define MSM_PARAM_CHIP_ID 0x03 39 #define MSM_PARAM_MAX_FREQ 0x04 40 #define MSM_PARAM_TIMESTAMP 0x05 41 #define MSM_PARAM_GMEM_BASE 0x06 42 #define MSM_PARAM_NR_RINGS 0x07 43 struct drm_msm_param { 44 __u32 pipe; 45 __u32 param; 46 __u64 value; 47 }; 48 #define MSM_BO_SCANOUT 0x00000001 49 #define MSM_BO_GPU_READONLY 0x00000002 50 #define MSM_BO_CACHE_MASK 0x000f0000 51 #define MSM_BO_CACHED 0x00010000 52 #define MSM_BO_WC 0x00020000 53 #define MSM_BO_UNCACHED 0x00040000 54 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 55 struct drm_msm_gem_new { 56 __u64 size; 57 __u32 flags; 58 __u32 handle; 59 }; 60 #define MSM_INFO_GET_OFFSET 0x00 61 #define MSM_INFO_GET_IOVA 0x01 62 #define MSM_INFO_SET_NAME 0x02 63 #define MSM_INFO_GET_NAME 0x03 64 struct drm_msm_gem_info { 65 __u32 handle; 66 __u32 info; 67 __u64 value; 68 __u32 len; 69 __u32 pad; 70 }; 71 #define MSM_PREP_READ 0x01 72 #define MSM_PREP_WRITE 0x02 73 #define MSM_PREP_NOSYNC 0x04 74 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 75 struct drm_msm_gem_cpu_prep { 76 __u32 handle; 77 __u32 op; 78 struct drm_msm_timespec timeout; 79 }; 80 struct drm_msm_gem_cpu_fini { 81 __u32 handle; 82 }; 83 struct drm_msm_gem_submit_reloc { 84 __u32 submit_offset; 85 __u32 or; 86 __s32 shift; 87 __u32 reloc_idx; 88 __u64 reloc_offset; 89 }; 90 #define MSM_SUBMIT_CMD_BUF 0x0001 91 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 92 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 93 struct drm_msm_gem_submit_cmd { 94 __u32 type; 95 __u32 submit_idx; 96 __u32 submit_offset; 97 __u32 size; 98 __u32 pad; 99 __u32 nr_relocs; 100 __u64 relocs; 101 }; 102 #define MSM_SUBMIT_BO_READ 0x0001 103 #define MSM_SUBMIT_BO_WRITE 0x0002 104 #define MSM_SUBMIT_BO_DUMP 0x0004 105 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP) 106 struct drm_msm_gem_submit_bo { 107 __u32 flags; 108 __u32 handle; 109 __u64 presumed; 110 }; 111 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 112 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 113 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 114 #define MSM_SUBMIT_SUDO 0x10000000 115 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | 0) 116 struct drm_msm_gem_submit { 117 __u32 flags; 118 __u32 fence; 119 __u32 nr_bos; 120 __u32 nr_cmds; 121 __u64 bos; 122 __u64 cmds; 123 __s32 fence_fd; 124 __u32 queueid; 125 }; 126 struct drm_msm_wait_fence { 127 __u32 fence; 128 __u32 pad; 129 struct drm_msm_timespec timeout; 130 __u32 queueid; 131 }; 132 #define MSM_MADV_WILLNEED 0 133 #define MSM_MADV_DONTNEED 1 134 #define __MSM_MADV_PURGED 2 135 struct drm_msm_gem_madvise { 136 __u32 handle; 137 __u32 madv; 138 __u32 retained; 139 }; 140 #define MSM_SUBMITQUEUE_FLAGS (0) 141 struct drm_msm_submitqueue { 142 __u32 flags; 143 __u32 prio; 144 __u32 id; 145 }; 146 #define DRM_MSM_GET_PARAM 0x00 147 #define DRM_MSM_GEM_NEW 0x02 148 #define DRM_MSM_GEM_INFO 0x03 149 #define DRM_MSM_GEM_CPU_PREP 0x04 150 #define DRM_MSM_GEM_CPU_FINI 0x05 151 #define DRM_MSM_GEM_SUBMIT 0x06 152 #define DRM_MSM_WAIT_FENCE 0x07 153 #define DRM_MSM_GEM_MADVISE 0x08 154 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 155 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 156 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 157 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 158 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 159 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 160 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 161 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 162 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 163 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 164 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 165 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 166 #ifdef __cplusplus 167 } 168 #endif 169 #endif 170