1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSM_DRM_H__ 20 #define __MSM_DRM_H__ 21 #include "drm.h" 22 #include "sde_drm.h" 23 #ifdef __cplusplus 24 #endif 25 #define MSM_PIPE_NONE 0x00 26 #define MSM_PIPE_2D0 0x01 27 #define MSM_PIPE_2D1 0x02 28 #define MSM_PIPE_3D0 0x10 29 #define MSM_PIPE_ID_MASK 0xffff 30 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 31 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 32 struct drm_msm_timespec { 33 __s64 tv_sec; 34 __s64 tv_nsec; 35 }; 36 #define HDR_PRIMARIES_COUNT 3 37 #define HDR_EOTF_SDR_LUM_RANGE 0x0 38 #define HDR_EOTF_HDR_LUM_RANGE 0x1 39 #define HDR_EOTF_SMTPE_ST2084 0x2 40 #define HDR_EOTF_HLG 0x3 41 #define DRM_MSM_EXT_HDR_METADATA 42 struct drm_msm_ext_hdr_metadata { 43 __u32 hdr_state; 44 __u32 eotf; 45 __u32 hdr_supported; 46 __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; 47 __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; 48 __u32 white_point_x; 49 __u32 white_point_y; 50 __u32 max_luminance; 51 __u32 min_luminance; 52 __u32 max_content_light_level; 53 __u32 max_average_light_level; 54 }; 55 #define DRM_MSM_EXT_HDR_PROPERTIES 56 struct drm_msm_ext_hdr_properties { 57 __u8 hdr_metadata_type_one; 58 __u32 hdr_supported; 59 __u32 hdr_eotf; 60 __u32 hdr_max_luminance; 61 __u32 hdr_avg_luminance; 62 __u32 hdr_min_luminance; 63 }; 64 #define MSM_PARAM_GPU_ID 0x01 65 #define MSM_PARAM_GMEM_SIZE 0x02 66 #define MSM_PARAM_CHIP_ID 0x03 67 #define MSM_PARAM_MAX_FREQ 0x04 68 #define MSM_PARAM_TIMESTAMP 0x05 69 struct drm_msm_param { 70 __u32 pipe; 71 __u32 param; 72 __u64 value; 73 }; 74 #define MSM_BO_SCANOUT 0x00000001 75 #define MSM_BO_GPU_READONLY 0x00000002 76 #define MSM_BO_CACHE_MASK 0x000f0000 77 #define MSM_BO_CACHED 0x00010000 78 #define MSM_BO_WC 0x00020000 79 #define MSM_BO_UNCACHED 0x00040000 80 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 81 struct drm_msm_gem_new { 82 __u64 size; 83 __u32 flags; 84 __u32 handle; 85 }; 86 struct drm_msm_gem_info { 87 __u32 handle; 88 __u32 pad; 89 __u64 offset; 90 }; 91 #define MSM_PREP_READ 0x01 92 #define MSM_PREP_WRITE 0x02 93 #define MSM_PREP_NOSYNC 0x04 94 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 95 struct drm_msm_gem_cpu_prep { 96 __u32 handle; 97 __u32 op; 98 struct drm_msm_timespec timeout; 99 }; 100 struct drm_msm_gem_cpu_fini { 101 __u32 handle; 102 }; 103 struct drm_msm_gem_submit_reloc { 104 __u32 submit_offset; 105 __u32 or; 106 __s32 shift; 107 __u32 reloc_idx; 108 __u64 reloc_offset; 109 }; 110 #define MSM_SUBMIT_CMD_BUF 0x0001 111 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 112 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 113 struct drm_msm_gem_submit_cmd { 114 __u32 type; 115 __u32 submit_idx; 116 __u32 submit_offset; 117 __u32 size; 118 __u32 pad; 119 __u32 nr_relocs; 120 __u64 relocs; 121 }; 122 #define MSM_SUBMIT_BO_READ 0x0001 123 #define MSM_SUBMIT_BO_WRITE 0x0002 124 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 125 struct drm_msm_gem_submit_bo { 126 __u32 flags; 127 __u32 handle; 128 __u64 presumed; 129 }; 130 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 131 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 132 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 133 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0) 134 struct drm_msm_gem_submit { 135 __u32 flags; 136 __u32 fence; 137 __u32 nr_bos; 138 __u32 nr_cmds; 139 __u64 bos; 140 __u64 cmds; 141 __s32 fence_fd; 142 }; 143 struct drm_msm_wait_fence { 144 __u32 fence; 145 __u32 pad; 146 struct drm_msm_timespec timeout; 147 }; 148 #define MSM_MADV_WILLNEED 0 149 #define MSM_MADV_DONTNEED 1 150 #define __MSM_MADV_PURGED 2 151 struct drm_msm_gem_madvise { 152 __u32 handle; 153 __u32 madv; 154 __u32 retained; 155 }; 156 #define DISPLAY_PRIMARIES_WX 0 157 #define DISPLAY_PRIMARIES_WY 1 158 #define DISPLAY_PRIMARIES_RX 2 159 #define DISPLAY_PRIMARIES_RY 3 160 #define DISPLAY_PRIMARIES_GX 4 161 #define DISPLAY_PRIMARIES_GY 5 162 #define DISPLAY_PRIMARIES_BX 6 163 #define DISPLAY_PRIMARIES_BY 7 164 #define DISPLAY_PRIMARIES_MAX 8 165 struct drm_panel_hdr_properties { 166 __u32 hdr_enabled; 167 __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; 168 __u32 peak_brightness; 169 __u32 blackness_level; 170 }; 171 struct drm_msm_event_req { 172 __u32 object_id; 173 __u32 object_type; 174 __u32 event; 175 __u64 client_context; 176 __u32 index; 177 }; 178 struct drm_msm_event_resp { 179 struct drm_event base; 180 struct drm_msm_event_req info; 181 __u8 data[]; 182 }; 183 #define DRM_MSM_GET_PARAM 0x00 184 #define DRM_MSM_GEM_NEW 0x02 185 #define DRM_MSM_GEM_INFO 0x03 186 #define DRM_MSM_GEM_CPU_PREP 0x04 187 #define DRM_MSM_GEM_CPU_FINI 0x05 188 #define DRM_MSM_GEM_SUBMIT 0x06 189 #define DRM_MSM_WAIT_FENCE 0x07 190 #define DRM_MSM_GEM_MADVISE 0x08 191 #define DRM_SDE_WB_CONFIG 0x40 192 #define DRM_MSM_REGISTER_EVENT 0x41 193 #define DRM_MSM_DEREGISTER_EVENT 0x42 194 #define DRM_MSM_RMFB2 0x43 195 #define DRM_EVENT_HISTOGRAM 0x80000000 196 #define DRM_EVENT_AD_BACKLIGHT 0x80000001 197 #define DRM_EVENT_CRTC_POWER 0x80000002 198 #define DRM_EVENT_SYS_BACKLIGHT 0x80000003 199 #define DRM_EVENT_SDE_POWER 0x80000004 200 #define DRM_EVENT_IDLE_NOTIFY 0x80000005 201 #define DRM_EVENT_PANEL_DEAD 0x80000006 202 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 203 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 204 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 205 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 206 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 207 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 208 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 209 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 210 #define DRM_IOCTL_SDE_WB_CONFIG DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) 211 #define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) 212 #define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) 213 #define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_RMFB2), unsigned int) 214 #ifdef __cplusplus 215 #endif 216 #endif 217 218