1/** @file 2* Multiple APIC Description Table (MADT) 3* 4* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. 5* Copyright (c) 2015, Hisilicon Limited. All rights reserved. 6* Copyright (c) 2015, Linaro Limited. All rights reserved. 7* 8* This program and the accompanying materials 9* 10* This program and the accompanying materials 11* are licensed and made available under the terms and conditions of the BSD License 12* which accompanies this distribution. The full text of the license may be found at 13* http://opensource.org/licenses/bsd-license.php 14* 15* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17* 18* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ 19* 20**/ 21 22#include "Hi1610Platform.h" 23 24#include <Library/AcpiLib.h> 25#include <Library/ArmLib.h> 26#include <Library/PcdLib.h> 27#include <IndustryStandard/Acpi.h> 28#include <Library/AcpiNextLib.h> 29 30// Differs from Juno, we have another affinity level beyond cluster and core 31// 0x20000 is only for socket 0 32#define PLATFORM_GET_MPID(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId)) 33 34// 35// Multiple APIC Description Table 36// 37#pragma pack (1) 38 39typedef struct { 40 EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; 41 EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; 42 EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; 43 EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1]; 44} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; 45 46#pragma pack () 47 48EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 49 { 50 ARM_ACPI_HEADER ( 51 EFI_ACPI_1_0_APIC_SIGNATURE, 52 EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, 53 EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 54 ), 55 // 56 // MADT specific fields 57 // 58 0, // LocalApicAddress 59 0, // Flags 60 }, 61 { 62 // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, 63 // GsivId, GicRBase, Mpidr) 64 // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of 65 // ACPI v5.1). 66 // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses 67 // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. 68 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 69 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 70 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), 71 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 72 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 73 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), 74 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 75 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 76 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), 77 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 78 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 79 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), 80 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 81 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 82 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), 83 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 84 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 85 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), 86 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 87 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 88 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), 89 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 90 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 91 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), 92 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 93 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 94 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), 95 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 96 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 97 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), 98 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 99 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 100 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), 101 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 102 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 103 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), 104 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 105 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 106 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), 107 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 108 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 109 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), 110 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 111 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 112 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), 113 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( 114 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 115 FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), 116 }, 117 118 EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), 119 { 120 EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), 121 } 122}; 123 124// 125// Reference the table being generated to prevent the optimizer from removing the 126// data structure from the executable 127// 128VOID* CONST ReferenceAcpiTable = &Madt; 129