1 /** @file
2 *
3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
4 * Copyright (c) 2016, Linaro Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16
17 #include "PcieInit.h"
18 #include <Library/UefiBootServicesTableLib.h>
19 #include <Library/PcdLib.h>
20
21 extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
22 extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
23 extern EFI_STATUS PciePortInit (UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
24
25 PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_PORT_NUM] =
26 {
27 //Port 0
28 {
29 0x0, //Portindex
30
31 {
32 PCIE_ROOT_COMPLEX, //PortType
33 PCIE_WITDH_X8, //PortWidth
34 PCIE_GEN3_0, //PortGen
35 }, //PortInfo
36
37 },
38
39 //Port 1
40 {
41 0x1, //Portindex
42 {
43 PCIE_ROOT_COMPLEX, //PortType
44 PCIE_WITDH_X8, //PortWidth
45 PCIE_GEN3_0, //PortGen
46 },
47
48 },
49
50 //Port 2
51 {
52 0x2, //Portindex
53 {
54 PCIE_ROOT_COMPLEX, //PortType
55 PCIE_WITDH_X8, //PortWidth
56 PCIE_GEN3_0, //PortGen
57 },
58
59 },
60
61 //Port 3
62 {
63 0x3, //Portindex
64 {
65 PCIE_ROOT_COMPLEX, //PortType
66 PCIE_WITDH_X8, //PortWidth
67 PCIE_GEN3_0, //PortGen
68 },
69
70 },
71 };
72
73 EFI_STATUS
PcieInitEntry(IN EFI_HANDLE ImageHandle,IN EFI_SYSTEM_TABLE * SystemTable)74 PcieInitEntry (
75 IN EFI_HANDLE ImageHandle,
76 IN EFI_SYSTEM_TABLE *SystemTable
77 )
78
79 {
80 UINT32 Port;
81 EFI_STATUS Status = EFI_SUCCESS;
82 UINT32 HostBridgeNum = 0;
83
84 for (HostBridgeNum = 0; HostBridgeNum < PCIE_HOST_BRIDGE_NUM; HostBridgeNum++)
85 {
86 for (Port = 0; Port < PCIE_MAX_PORT_NUM; Port++)
87 {
88 if (!((((PcdGet32(PcdPcieRootBridgeMask) >> (4 * HostBridgeNum))) >> Port) & 0x1))
89 {
90 continue;
91 }
92
93 Status = PciePortInit(HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
94 if(EFI_ERROR(Status))
95 {
96 DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
97 }
98
99 }
100 }
101
102 return EFI_SUCCESS;
103 }
104