1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cortex_a53.h> 11#include <cortex_a57.h> 12#include <cortex_a72.h> 13#include <v2m_def.h> 14#include "../juno_def.h" 15 16 17 .globl plat_reset_handler 18 .globl plat_arm_calc_core_pos 19 20#define JUNO_REVISION(rev) REV_JUNO_R##rev 21#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev 22#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ 23 jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) 24 25 /* -------------------------------------------------------------------- 26 * Helper macro to jump to the given handler if the board revision 27 * matches. 28 * Expects the Juno board revision in x0. 29 * -------------------------------------------------------------------- 30 */ 31 .macro jump_to_handler _revision, _handler 32 cmp r0, #\_revision 33 beq \_handler 34 .endm 35 36 /* -------------------------------------------------------------------- 37 * Helper macro that reads the part number of the current CPU and jumps 38 * to the given label if it matches the CPU MIDR provided. 39 * 40 * Clobbers r0. 41 * -------------------------------------------------------------------- 42 */ 43 .macro jump_if_cpu_midr _cpu_midr, _label 44 ldcopr r0, MIDR 45 ubfx r0, r0, #MIDR_PN_SHIFT, #12 46 ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 47 cmp r0, r1 48 beq \_label 49 .endm 50 51 /* -------------------------------------------------------------------- 52 * Platform reset handler for Juno R0. 53 * 54 * Juno R0 has the following topology: 55 * - Quad core Cortex-A53 processor cluster; 56 * - Dual core Cortex-A57 processor cluster. 57 * 58 * This handler does the following: 59 * - Implement workaround for defect id 831273 by enabling an event 60 * stream every 65536 cycles. 61 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 62 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 63 * -------------------------------------------------------------------- 64 */ 65func JUNO_HANDLER(0) 66 /* -------------------------------------------------------------------- 67 * Enable the event stream every 65536 cycles 68 * -------------------------------------------------------------------- 69 */ 70 mov r0, #(0xf << EVNTI_SHIFT) 71 orr r0, r0, #EVNTEN_BIT 72 stcopr r0, CNTKCTL 73 74 /* -------------------------------------------------------------------- 75 * Nothing else to do on Cortex-A53. 76 * -------------------------------------------------------------------- 77 */ 78 jump_if_cpu_midr CORTEX_A53_MIDR, 1f 79 80 /* -------------------------------------------------------------------- 81 * Cortex-A57 specific settings 82 * -------------------------------------------------------------------- 83 */ 84 mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 85 (CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT)) 86 stcopr r0, CORTEX_A57_L2CTLR 871: 88 isb 89 bx lr 90endfunc JUNO_HANDLER(0) 91 92 /* -------------------------------------------------------------------- 93 * Platform reset handler for Juno R1. 94 * 95 * Juno R1 has the following topology: 96 * - Quad core Cortex-A53 processor cluster; 97 * - Dual core Cortex-A57 processor cluster. 98 * 99 * This handler does the following: 100 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 101 * 102 * Note that: 103 * - The default value for the L2 Tag RAM latency for Cortex-A57 is 104 * suitable. 105 * - Defect #831273 doesn't affect Juno R1. 106 * -------------------------------------------------------------------- 107 */ 108func JUNO_HANDLER(1) 109 /* -------------------------------------------------------------------- 110 * Nothing to do on Cortex-A53. 111 * -------------------------------------------------------------------- 112 */ 113 jump_if_cpu_midr CORTEX_A57_MIDR, A57 114 bx lr 115 116A57: 117 /* -------------------------------------------------------------------- 118 * Cortex-A57 specific settings 119 * -------------------------------------------------------------------- 120 */ 121 mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) 122 stcopr r0, CORTEX_A57_L2CTLR 123 isb 124 bx lr 125endfunc JUNO_HANDLER(1) 126 127 /* -------------------------------------------------------------------- 128 * Platform reset handler for Juno R2. 129 * 130 * Juno R2 has the following topology: 131 * - Quad core Cortex-A53 processor cluster; 132 * - Dual core Cortex-A72 processor cluster. 133 * 134 * This handler does the following: 135 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 136 * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 137 * 138 * Note that: 139 * - Defect #831273 doesn't affect Juno R2. 140 * -------------------------------------------------------------------- 141 */ 142func JUNO_HANDLER(2) 143 /* -------------------------------------------------------------------- 144 * Nothing to do on Cortex-A53. 145 * -------------------------------------------------------------------- 146 */ 147 jump_if_cpu_midr CORTEX_A72_MIDR, A72 148 bx lr 149 150A72: 151 /* -------------------------------------------------------------------- 152 * Cortex-A72 specific settings 153 * -------------------------------------------------------------------- 154 */ 155 mov r0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 156 (CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT)) 157 stcopr r0, CORTEX_A72_L2CTLR 158 isb 159 bx lr 160endfunc JUNO_HANDLER(2) 161 162 /* -------------------------------------------------------------------- 163 * void plat_reset_handler(void); 164 * 165 * Determine the Juno board revision and call the appropriate reset 166 * handler. 167 * -------------------------------------------------------------------- 168 */ 169func plat_reset_handler 170 /* Read the V2M SYS_ID register */ 171 ldr r0, =(V2M_SYSREGS_BASE + V2M_SYS_ID) 172 ldr r1, [r0] 173 /* Extract board revision from the SYS_ID */ 174 ubfx r0, r1, #V2M_SYS_ID_REV_SHIFT, #4 175 176 JUMP_TO_HANDLER_IF_JUNO_R(0) 177 JUMP_TO_HANDLER_IF_JUNO_R(1) 178 JUMP_TO_HANDLER_IF_JUNO_R(2) 179 180 /* Board revision is not supported */ 181 no_ret plat_panic_handler 182 183endfunc plat_reset_handler 184 185 /* ----------------------------------------------------- 186 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 187 * Helper function to calculate the core position. 188 * ----------------------------------------------------- 189 */ 190func plat_arm_calc_core_pos 191 b css_calc_core_pos_swap_cluster 192endfunc plat_arm_calc_core_pos 193